• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.68-75
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• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• Publications of The Korean Astronomical Society
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• v.34 no.3
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• pp.49-65
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• 2019

We investigate the provenance and the changes in the timekeeping system focusing on official records such as almanacs and textbooks published by the government after the solar calendar was introduced. We found that the solar calendar and the 12-hour clock time first appeared in 1884 during Joseon dynasty, at that time the solar calendar was used at the open port in Busan to facilitate the exchanges with Japan. The 12-hour clock time first appeared in the 『Hansung Sunbo』 published by the government in 1884. We also found that the Joseon dynasty also used 12 diǎnzhōng or 12 diǎn. In addition, the term of the 'Sigan' first appeared in the first official academic textbook in August 1895, and the chapter related to time contained the information about 12-hour clock time instead of the 12 Shi. In 1908, the meaning of the solar time, the equation of time, and the differences in longitude with the adoption of Korean Standard Time were introduced. Meanwhile, the 24-hour clock time was first introduced in Joseon and applied to railway times in 1907. The 1946 almanac, the first issue after liberation, used the 12-hour clock time which uses 'Sango', 'Hao' and the 24-hour clock time started to be used from the following year and is still used to this day. Finally, the 12-hour clock time, which was introduced around 1884, was enacted as Article 44 of the law in 1900 and was revised again in 1905 and 1908. In Korea, the terms related to the time in the current astronomical calendar system were newly defined around 1884, 1896, and 1908, and gradually standardized through the establishment of laws.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.277-280
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• 2008

Enhancing the positioning precision is the primary pursuit of GPS users. To achieve this goal, most studies have focused on the relationship between GPS receiver clock errors and GPS positioning precision. This study utilizes undifferentiated phase data to calculate GPS clock errors and to compare with the frequency of cesium clock directly, thus verifying estimated clock errors by the method used in this paper. The relative frequency offsets from this paper and from National Standard Time and Frequency Laboratory of Taiwan match to $1.5{\times}10^{12}$ in the frequency instability, suggesting that the proposed technique has reached a certain level of quality. The built-in quartz clocks in the GPS receivers yield relative frequency offsets that are 3 to 4 orders higher than those of rubidium clocks. The frequency instability of the quartz clocks is on average two orders worse than that of the rubidium clock. Using the rubidium clock instead of the quartz clock, the horizontal and vertical positioning accuracies were improved by 26-78% (0.6-3.6 mm) and 20-34% (1.3-3.0 mm), respectively, for a short baseline. These improvements are 7-25% (0.3-1.7 mm) and 11% (1.7 mm) for a long baseline. Our experiments show that the frequency instability of clock, rather than relative frequency offset, is the governing factor of positioning accuracy.

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.348-357
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• 2007

One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or turn on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.593-599
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• 2007

PC based DVR replaces existing analog CCTV system therefore expands the field and DVR is used for monitoring and security so it requires exact time(clock). But DVR system can't maintains exact clock causing several reasons. For providing exact time information we should use additional system. For economical and usable environment, using GPS system is most suitable suggested solution than use WAN(Wide Area Network). Therefore in this paper for analysis the result of PC based DVR's system clock using GPS system, 1) clock source receiving module that receives the clock form GPS satellite and 2) GPSW H/W units that provide clock source to PC Based DVR 3)Daemon software named PCSW which adjust PC's clock so system could reduced the clock difference with UTC clock and measured the result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12A
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• pp.1128-1135
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• 2010

A wireless positioning system using ultra-wideband (UWB) for indoor wireless positioning uses ranging data in order to accurately estimate location. Commonly, ranging uses time of arrival (TOA), time difference of arrival (TDOA) based on arrival time. The most fundamental issue in the ranging for wireless positioning is to obtain clock synchronization among the sensor nodes and to correct an error caused by the relative clock offset from each node. In this paper, we propose ranging and positioning technique using common clock in order to solve both clock synchronization and clock offset problems. To verify the performance of proposed, we simulated ranging and positioning in channel model introduced by IEEE 802.15.4a Task Group and then results show that location estimation is unaffected by clock offset.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.395-400
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• 2006

Among the various error sources in positioning and navigation, the paper focuses on the modeling and prediction of receiver clock bias and then tries to achieve positioning based on simulated and predicted clock bias. With the SA off, it is possible to model receiver clock bias more accurately. We selected several types of GNSS receivers for test using ARMA model. To facilitate prediction with short and limited sample pseudorange observations, AR and ARMA are compared, and the improved AR model is presented to model and predict receiver clock bias based on previous solutions. Our work extends to clock bias prediction and positioning based on predicted clock bias using only 3 satellites that is usually the case under urban canyon situation. In contrast to previous experiences, we find that a receiver clock bias can be well modeled using adopted ARMA model. Test has been done on various types of GNSS receivers to show the validation of developed model. To further develop this work, we compare solution conditions in terms of DOP values when point positioning is conducted using 3 satellites to simulate urban positioning environment. When condition allows, height component is derived from other ways and can be set as known values. Given this condition, location is possible using less than 2 GNSS satellites with fixed height. Solution condition is also discussed for this background using mode of constrained positioning. We finally suggest an effective predictive time span based on our test exploration under varied conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).