• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.1001-1008
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• 1991

.In this paper the efficient clock recovery algorithm is proposed to regenerate the manchester code at the system using the Manchester encoding scheme such as LAN. Mobile communication and digital communication systems. The proposed clock recovery circuit recovers the clock using the two times of the same original transmitted frequency can be completely recovered. The implementation of the proposed clock recovery circuit and the interpretation of test results prove the validity of the proposed algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1264-1274
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• 1999

본 논문에서는 분산된 클록들을 주기적으로 동기화 시키는 분산 실시간 시스템에서 시간적 제약을 만족시키기 위한 정적/동적 시간 제약(timing constraint) 변환 기법을 제안한다. 전형적인 이산클록동기화(discrete clock synchronization) 알고리즘은 클록의 값을 순간적으로 조정하여 클록의 시간이 불연속적으로 진행한다. 이러한 시간상의 불연속성은 시간적 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다.클록 시간의 불연속성을 피하기 위해 일반적으로 연속클록동기화(continuous clock synchronization) 기법이 제안되고 있지만 소프트웨어적으로 구현되면 많은 오버헤드를 유발시키는 문제점이 있다. 본 논문에서는 시간적 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였으며, 이를 통해 기존의 이산클록동기화 알고리즘을 수정하지 않고서도 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있도록 하였다. 아울러 DCT에 의해 이산클록동기화 하에서 생성된 태스크 스케쥴이 연속클록동기화에 의해 생성된 스케쥴과 동일함을 증명하여 DCT의 동작이 이론적으로 정확함을 증명하였다.또한 분산 실시간 시스템에서 지역 클록(local clock)이 기준 클록과 완벽하게 일치하지 않아서 발생하는 스케쥴링상의 문제점을 다루었다. 이를 위해 먼저 두 가지의 스케쥴링 가능성, 지역적 스케쥴링 가능성(local schedulability)과 전역적 스케쥴링 가능성(global schedulability)을 정의하고, 이를 위해 시간적 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation) 기법을 제안하였다. SCT를 통해 지역적으로 스케쥴링 가능한 태스크는 전역적으로 스케쥴링이 가능하므로, 단지 지역적 스케쥴링 가능성만을 검사하면 스케쥴링 문제를 해결할 수 있도록 하였고 이를 수학적으로 증명하였다.Abstract In this paper, we present static and dynamic constraint transformation techniques for ensuring timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. Traditional discrete clock synchronization algorithms that adjust local clocks instantaneously yield time discontinuities. Such time discontinuities lead to the loss or the gain of events, thus raising serious run-time faults.While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much run-time overhead to be implemented in software. We propose a dynamic constraint transformation (DCT) technique which can solve the problem without modifying discrete clock synchronization algorithms. We formally prove the correctness of the DCT by showing that the DCT with discrete clock synchronization generates the same task schedule as the continuous clock synchronization.We also investigate schedulability problems that arise when imperfect local clocks are used in distributed real-time systems. We first define two notions of schedulability, global schedulability and local schedulability, and then present a static constraint transformation (SCT) technique. The SCT ensures that it is sufficient to check the schedulability of a task locally in a node with a local clock, since the global schedulability of the task is derived from its local schedulability through SCT. We formally prove the correctness of SCT.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.1
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• pp.58-63
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• 2010

In this paper, we propose a simple technique for the detection of a frequency jump in the GPS clock behavior. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term and a non-periodic frequency drift in the short term, showing a sudden frequency jump occasionally. As satellite clock anomalies influence on GPS measurements, it requires to develop a real time technique for the detection of the clock anomaly on the real-time GPS precise point positioning. The proposed technique is based on Teager energy which is mainly used in the field of various signal processing for the detection of a specific signal or symptom. Therefore, we employed the Teager energy for the detection of the jump phenomenon of GPS satellite atomic clocks, and it showed that the proposed clock anomaly detection strategy outperforms a conventional detection methodology.

• The Journal of Korean Society for School & Community Health Education
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• v.13 no.2
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• pp.107-118
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• 2012

Backgrounds: In order to prevent dental injuries that often occur in child and adolescent, it is intended to investigate and assess actual state of the injury development, present epidemiological background, and consider and discuss for preparing preventive means against the injury development. Purpose: It was attempted to understand major features of dental injuries developing in child and adolescent and indentify high risk factors of dental injuries in child and adolescent. Methods: In this study, 523 cases of computerized data collected as disease entities of dental injuries among 1-18 years old patient visiting S university hospital located in Seoul in 2009 were analyzed and following results were obtained. Results: It was found that the ratio of dental injuries by genders in child and adolescent was 66.14% of male and 33.86% of female. It was shown also that causes of dental injuries by ages were more in order of falling, bumping, chewing, traffic accident, sports, violence, and crash. In addition places where dental injuries occur by ages were home in less than 5 year old group, park, playground, and play yard in 6-11 year old group, park, playground, and play yard also in 12-14 year old group, and stairs, road, and outdoor places such as mountain climbing, beach, and camping in 15-18 year old group. It was found that time rages when dental injuries in child and adolescent often develop were 15-19 o'clock for falling, 15-19 o'clock for crash, 15-19 o'clock for bumping, 19-03 o'clock for violence, 15-19 o'clock for traffic accident, 15-19 o'clock for sports activity, and 15-19 o'clock for chewing. Conclusion: Background of dental injury inducing factors are very complicated and diversified, so deep study and analysis are required for its prediction. Therefore, it seems necessary to identify risk factors by phases such as before, at, and after accident, establish strategies to reduce injury development, and develop and utilize necessary programs.

• Journal of Korean Biological Nursing Science
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• v.18 no.4
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• pp.305-317
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• 2016

Purpose: Recent studies demonstrated disruption of the circadian clock gene is associated with the development of obesity and metabolic syndrome. Obesity is often caused by the high calorie intake, In addition, the chronic stress tends to contribute to the increased risk for obesity. To evaluate the molecular mechanisms, we examined the expression of circadian clock genes in high fat diet-induced mice models with the chronic stress. Methods: C57BL/6J mice were fed with a 45% or 60% high fat diet for 8 weeks. Daily immobilization stress was applied to mice fed with a 45% high fat for 16 weeks. We compared body weight, food consumption, hormone levels and metabolic variables in blood. mRNA expression levels of metabolic and circadian clock genes in both fat and liver were determined by quantitative RT-PCR. Results: The higher fat content induced more severe hyperglycemia, hyperlipidemia and hyperinsulinemia, and these results correlated with their relevant gene expressions in fat and liver tissues. Chronic stress had only minimal effects on metabolic variables, but it altered the expression patterns of metabolic and circadian clock genes. Conclusion: These results suggest that the fat metabolism regulates the function of the circadian clock genes in peripheral tissues, and stress hormones may contribute to its regulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.30-36
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• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.