• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.208-222
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• 2015

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• ETRI Journal
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• v.36 no.6
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.626-635
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• 2012

Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.383-390
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• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.257-266
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• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• ETRI Journal
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• v.32 no.6
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• pp.854-862
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• 2010

One-way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real-time and streaming services such as voice-over-Internet-protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global-positioning system (GPS) or network time protocol. In clock-synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter-packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.