JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

  • Song, Sung-Gun (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Park, Seong-Mo (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Lee, Jeong-Gun (Dept. of Computer Engineering, Hallym University) ;
  • Oh, Myeong-Hoon (Electronics and Telecommunications Research Institute(ETRI))
  • Received : 2014.07.28
  • Accepted : 2015.01.23
  • Published : 2015.04.30
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Abstract

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

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