Journal of Computing Science and Engineering

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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Design Methodologies for Reliable Clock Networks

  • Joo, Deokjin (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kang, Minseok (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Taewhan (Department of Electrical Engineering and Computer Science, Seoul National University)
  • Received : 2012.10.30
  • Accepted : 2012.11.16
  • Published : 2012.12.30
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Abstract

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

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References

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