1 |
D. Saha and S. Sur-Kolay, "SoC: a real platform for IP reuse, IP infringement, and IP protection," VLSI Design, vol. 2011, Article ID 731957, 10 pages, Jan. 2011.
|
2 |
R. Saleh, S. Wilton, S. Mirabbasi, and et al., "System-on-Chip: Reuse and Integration," Proc. of the IEEE, Vol.94, No.6, pp.1050-1069, Jun., 2006.
DOI
ScienceOn
|
3 |
D.G. Messerschmitt, "Synchronization in Digital System Design," IEEE Journal on Selected Areas in Communications, Vol.8, No.8, pp.1404-1419, Oct., 1990.
DOI
ScienceOn
|
4 |
P. Teehan, M. Greenstreet and G. Lemieux, "A survey and taxonomy of GALS design styles," IEEE Design & Test of Computers, Vol.24, No.5, pp.418-428, Oct., 2007.
DOI
ScienceOn
|
5 |
A. Chakraborty and M.R. Greenstreet, "Efficient self-timed interfaces for crossing clock domains," IEEE Int'l Symp. on Asynchronous Circuits and Systems, pp.78-88, May, 2003.
|
6 |
Y. Semiat and R. Ginosar, "Timing measurements of synchronization circuits," IEEE Int'l Symp. on Asynchronous Circuits and Systems, pp.68-77, May, 2003.
|
7 |
L.R. Dennison, W.J. Dennison and D. Xanthopolous, "Low-latency plesiochronous data retiming," IEEE Int'l Conf. on Adv. Res. in VLSI, pp.304-315, Mar., 1995.
|
8 |
R. Kol and R. Ginosar, "Adaptive Synchronization for Multi-Synchronous Systems," ICCD, pp.188-198, 1998.
|
9 |
L.F.G. Sarmenta, G.A. Pratt and S.A. Ward, "Rational clocking," IEEE Int'l Conf. on VLSI in Computers and Processors, pp.271-278, Oct., 1995.
|
10 |
W.J. Dally and J.W. Poulton, Digital Systems Engineering, Cambridge, 1998.
|
11 |
U. Frank and R. Ginosar "A Predictive Synchronizer for Periodic Clock Domains," Journal of Formal Methods in System Design archive, Vol.28, No.2, pp.171-186, Mar., 2006.
DOI
|
12 |
A.J. Martin, "Asynchronous Techniques for System-on-Chip Design," Proc. of the IEEE, Vol.94, No.6, pp.1089-1120, Jun., 2006.
DOI
ScienceOn
|
13 |
L.S. Kim, R. Cline, and R.W. Dutton, ''Metastability of CMOS Latch/Flip-Flop," Journal of Solid-State Circuits, Vol.25, No.4, pp.942-951, Aug., 1990.
DOI
ScienceOn
|
14 |
R. Ginosar, "Fourteen ways to fool your synchronizer," IEEE Int'l Symp. on Asynchronous Circuits and Systems, pp.89-96, May, 2003.
|
15 |
M.H. Oh and S.W. Kim, "Asynchronous 2-phase protocol based on ternary encoding for on-chip interconnect," ETRI Journal, Vol.33, No.5, pp.822-825, Oct., 2011.
DOI
|
16 |
D.J. Kinniment and A. Yakovlev, "Low latency synchronization through speculation," Workshop. on Power and Timing Modeling, Optimization and Simulation, pp.278-288, Sep., 2004.
|
17 |
S.J. Kim, J.G. Lee and K. Kim, "A parallel flop synchronizer for bridging asynchronous clock domains," IEEE Conf. on Asia Pacific-ASIC, pp.184-187, Aug. , 2004.
|
18 |
A. chakraborty and M.R. Greenstreet, "A minimal source-synchronous interface," IEEE Int'l Conf. on ASIC/SOCI, pp.443-447, Sept., 2002.
|
19 |
G.N. Pham and K.C. Schmitt, "A high throughput, asynchronous, dual port FIFO memory implemented in ASIC technology," IEEE Int'l Conf. on ASIC and Exhibition, pp.P3-1.1-1.4, Sep., 1989.
|
20 |
T. Chelcea and S.M. Nowick, "Robust interfaces for mixed-timing systems with application to latency-insensitive protocols," ACM/IEEE Conf. on Design Automation, pp.21-26, 2001.
|
21 |
R. Mullins and S. Moore, "Demystifying datadriven and pausible clocking schemes," IEEE Int'l Symp. on Asynchronous Circuits and Systems, pp.175-185, Mar, 2007.
|
22 |
K.Y. Yun and R.P. Donohue, "Pausible clockingbased heterogeneous systems," IEEE Transactions on VLSI Systems, Vol.7, No.4, pp.482-488, Dec., 1999.
DOI
ScienceOn
|
23 |
D.S. Bormann and P.Y.K. Cheung, "Asynchronous wrapper for heterogeneous systems," IEEE Int'l Conf. on Computer Design, pp.307-314, Oct., 1997.
|
24 |
C.K. Ong, M.T. Mustaffa, and L.H Goh, "Asynchronous to synchronous: A design methodology," IEEE Symp. on Industrial Electronics and Applications, pp.255-260, Sept., 2011.
|
25 |
P. Dudek, S. Szczepanski and J.V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a vernier delay line," IEEE J. Solid-State Circuits, Vol.35, No.2, pp.240-246, Feb., 2000.
DOI
ScienceOn
|
26 |
M.H. Oh, Y.W. Kim, S.H. Kwak, et al., "Architectural design issues on a clockless 32-bit processor using an asynchronous HDL," ETRI Journal, Vol.35, No.3, pp.480-490, Jun., 2013.
DOI
ScienceOn
|