• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.53 no.8
• /
• pp.517-524
• /
• 2004

In this paper, a novel zero-voltage-switching(ZVS) resonant DC-DC converter is proposed. It is composed of two symmetrical active-clamped circuits, the converter can be achieve ZVS in each switches. Also, active clamp capacitor ratios($\alpha$) of proposed circuit can be reduce a peak stress of switching voltage for each main switch. Simulation results using Pspice 9.2 ver and $C^{++}$ characteristic analysis show a provement for the validity of theoretical analysis. The analysis of the proposed Current-Fed Push Pull type DC-DC converter is generally described by using normalized parameter, and achieved an evaluated characteristic values which is needed to design a circuit. We confirm a rightfulness theoretical analysis by comparing a theoretical values and experimental values obtained from experiment using MOSFET as switching devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.4
• /
• pp.261-266
• /
• 2018

When the clamp meter approaches the electric path where current is flowing, leakage current can be measured at a distance from the electric current because the induced current increases as the magnitude of the current increases and approaches nearer to the electric path. Therefore, measurements were carried out from a distance to avoid this effect. In addition, the measured values differ depending on the location of the power line that penetrates the ZCT of the clamp meter, thus measurements were performed at a location where this effect was minimized. The fraction of compliant branch circuits, whose leakage current was lower than 1.00 mA, was found to be 69.0% out of the total of 439 branch circuits, while the percentage of compliant branch circuits having an insulation resistance higher than $0.20M{\Omega}$ was found to be 93.2%. The reason why the percentage of compliant branch circuits with low leakage current was low might be due to the inclusion of capacitive leakage current in the total measured leakage current.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2003.11a
• /
• pp.311-314
• /
• 2003

In this paper, proposed circuit proposes that Active-Clamp-Circuits basis of a current-fed inverter linked type high frequency resonant dc-dc converter of conventional. and the paper the most of characteristics of the reduced high voltage stress main switches with active clamp circuits and output current constant with the resonant part consists of L, C resonant tank circuit. Also, the capacitor (C$_1$, C$_2$) connected in switches are a common using by resonance capacitor and ZVS capacitor. and circuit analysis used state equation of each part modes. Also we conform a rightfulness theoretical analysis by comparing a parameters values and simulation values obtained from simulation using Power MOS-FET as switching devices.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.3
• /
• pp.366-372
• /
• 1998

A high efficiency interleaved active clamp forward converter with self driven synchronous rectifiers for a modular power processor is presented. To simplify the gate drive circuits, N-P MOSFETs coupled active clamp method is used. An efficiency about 90% for the load range of 50-100% is achieved. The details of design for the power stage and current mode control circuit are provided, and also some experimental results are given.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.227-231
• /
• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.2 no.2
• /
• pp.202-215
• /
• 2013

This paper proposes a SEPIC-input, self-driven, active clamp ZVS converter, where an auxiliary winding and a RC delay circuit are employed to drive the active clamp switch and to achieve asymmetrical duty control without any other extra circuits. Based on the fixed dead time and the resonance between capacitors and inductors, both the main switch and the auxiliary switch can rule the ZVS operation. Detailed operation modes are presented to illustrate the self-driven and ZVS principles. Furthermore, an accurate state-space model and the transfer functions of the proposed converter have been presented and analyzed in order to optimize dynamic performance. The model provides efficient prediction of converter operations. Experimental results, based on a prototype with 80V input and 15V/20A output, are discussed to verify the transient and steady performance of the proposed converter.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.56-61
• /
• 2018

In this paper, a new type of active snubber was proposed to lower the excessive rated voltage of the clamp capacitor which was a problem in the conventional circuit by applying auxiliary winding into the active snubber. A simplified equivalent circuit of the proposed snubber was derived by applying it to QR flyback converter, and the equivalent circuits for each switch state was shown under the steady-state condition. In addition, the maximum voltage of the clamp capacitor as well as the main switch was found by using the steady-state equations. In particular, it was found that the clamp capacitor voltage could be controlled by the auxiliary winding ratio. In order to verify the utility and practicality of the proposed converter with auxiliary winding type active snubber circuit, a prototype with an output voltage of 19V and a maximum load current of 6A was produced and the results were reported.

• Proceedings of the KIEE Conference
• /
• 2003.10b
• /
• pp.227-231
• /
• 2003

In This paper, A novel zero-voltage-switching(ZVS) resonant DC-DC converter is proposed. it is composed of two symmetrical active-clamped circuits, The converter can achieve each switchs ZVS. proposed circuit is active clamp capacitor Ratios can be reduce switching voltage stress of each main switch. Simulation results using Pspice ver 9.2 show that the prove the validity of theoretical analysis.

• Journal of Power Electronics
• /
• v.2 no.3
• /
• pp.199-205
• /
• 2002

This paper compares three kinds of soft-switching circuits from viewpoints of surge suppression, load characteristic, and power efficiency for a tapped-inductor buck converter with low voltage and high current. As a result, these soft-switching techniques have achieved much higher efficiency of 80 % when compared with a hard-switching buck converter for the output condition of 1V and 20A.

• ETRI Journal
• /
• v.37 no.1
• /
• pp.97-106
• /
• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).