• Journal of IKEEE
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• v.26 no.1
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• pp.83-88
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• 2022

With high performance and wide application, a CNTFET has been attracting a lot of attention as a next-eneration semiconductor, but the manufacturing process of CNTFET has not been mature enough, which makes commercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and to increase the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variation according to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whose performance variation is less sensitive to partial CNT density are selected among the six transistors constituting the SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when the CNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, the deviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delay is increased by more than 8 time.

• Convergence Security Journal
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• v.22 no.5
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• pp.3-9
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• 2022

Recently, in order to build a cyber physical system(CPS) that is a technology related to the 4th industry, the construction of the virtual control system for physical model and control circuit simulation is increasingly required in various industries. It takes a lot of time and money to convert documents that are not electronically documented through direct input. For this, it is very important to digitize a large number of drawings that have already been printed through object recognition using artificial intelligence. In this paper, in order to accurately recognize objects in drawings and to utilize them in various applications, a recognition technique using artificial intelligence by analyzing the characteristics of objects in drawing was proposed. In order to improve the performance of object recognition, each object was recognized and then an intermediate file storing the information was created. And the recognition rate of the next recognition target was improved by deleting the recognition result from the drawing. In addition, the recognition result was stored as a standardized format document so that it could be utilized in various fields of the control system. The excellent performance of the technique proposed in this paper was confirmed through the experiments.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.334-334
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• 2013

In the past decade, the infrared detectors based on intersubband transition in quantum dots (QDs) have attracted much attention due to lower dark currents and increased lifetimes, which are in turn due a three-dimensional confinement and a reduction of scattering, respectively. In parallel, focal plane array development for infrared imaging has proceeded from the first to third generations (linear arrays, 2D arrays for staring systems, and large format with enhanced capabilities, respectively). For a step further towards the next generation of FPAs, it is envisioned that a two-dimensional metal hole array (2D-MHA) structures will improve the FPA structure by enhancing the coupling to photodetectors via local field engineering, and will enable wavelength filtering. In regard to the improved performance at certain wavelengths, it is worth pointing out the structural difference between previous 2D-MHA integrated front-illuminated single pixel devices and back-illuminated devices. Apart from the pixel linear dimension, it is a distinct difference that there is a metal cladding (composed of a number of metals for ohmic contact and the read-out integrated circuit hybridization) in the FPA between the heavily doped gallium arsenide used as the contact layer and the ROIC; on the contrary, the front-illuminated single pixel device consists of two heavily doped contact layers separated by the QD-absorber on a semi-infinite GaAs substrate. This paper is focused on analyzing the impact of a two dimensional metal hole array structure integrated to the back-illuminated quantum dots-in-a-well (DWELL) infrared photodetectors. The metal hole array consisting of subwavelength-circular holes penetrating gold layer (2DAu-CHA) provides the enhanced responsivity of DWELL infrared photodetector at certain wavelengths. The performance of 2D-Au-CHA is investigated by calculating the absorption of active layer in the DWELL structure using a finite integration technique. Simulation results show the enhanced electric fields (thereby increasing the absorption in the active layer) resulting from a surface plasmon, a guided mode, and Fabry-Perot resonances. Simulation method accomplished in this paper provides a generalized approach to optimize the design of any type of couplers integrated to infrared photodetectors.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1034-1046
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• 2011

In this paper, a design and fabrication of 40 W power amplifier for the X-band using load-pull measurement of GaN HEMT chip are presented. The adopted active device for power amplifier is GaN HEMT chip of TriQuint company, which is recently released. Pre-matched fixtures are designed in test jig, because the impedance range of load-pull tuner is limited at measuring frequency. Essentially required 2-port S-parameters of the fixtures for extraction optimal input and output impedances is obtained by the presented newly method. The method is verified in comparison of the extracted optimal impedances with data sheet. The impedance matching circuit for power amplifier is designed based on EM co-simulation using the optimal impedances. The fabricated power amplifier with 15${\times}$17.8 $mm^2$ shows the efficiency above 35 %, the power gain of 8.7~8.3 dB and the output power of 46.7~46.3 dBm at 9~9.5 GHz with pulsed-driving width of 10 usec and duty of 10 %.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.120-130
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• 1999

In this paper, we show that the instantaneous phase current of the bifiler-wound hybrid stepping motor is dependent of lead angle and that the information of motor position is obtained from the instantaneous phase current at ${\pi}/2$ by the theoretical formular and its computer simulation results. From the facts, we design the microcontroller-based motor position sensorless controller of optimal lead angle, which generates the excitation pulses for the closed-loop drives. The controller is consist of microcontroller which has the function of A/D converter, programmable input/output timer, and the transfer table which has the values of optimal lead angle depending on motor velocity, and ROM which has the transfer table of the values of lead angle depending on velocity of motor and the values of instantaneous phase current at ${\pi}/2$. From the design of microcontroller-based controller, we minimize the external interface circuit and obtain flexibility by changing the contents of ROM transfer tables and the control software. We confirm that the designed controller drives the bifilar-wound hybrid stepping motor is the mode of optimal lead angle by comparing the instananeous phase current experimental results and computer simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.53-61
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• 2014

In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

• Journal of the Korean Society for Railway
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• v.16 no.6
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• pp.528-533
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• 2013

To improve the efficiency and safety of railway systems, the train control system has considerably evolved from the ground-equipment-based control system (e.g. track circuit, interlocking system, etc.) into the on-board-equipment-based control system. In addition, this train control system enables the rolling stock to intelligently control the trackside facilities by introducing information and communication technologies (ICT). Accordingly, since the ICT-based train control system simplifies the railway system (i.e. the heavy ground-equipment can be removed), an efficient and cost-effective railway system can be realized. In this paper, we perform a feasibility test of the ICT-based train control system using a simulation. To this end, we implement a test-bed consisting of prototype machines of on-board/ground equipment and introduce an integrated operation scenario for the train control. The simulation results satisfy all the requirements of train operation according to the scenario and show the effectiveness of the proposed train control system.

• Journal of the Korean Electrochemical Society
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• v.1 no.1
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• pp.40-44
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• 1998

The LAPS device of fast response and high sensitivity, based on electrochemical potential difference, and its system were fabricated for the precise measurement of pH changes and its characteristic were investigated. The electrostatic variation characteristics of LAPS according to the pH changes and parameters in the device were verified through a simulation using LAPS equivalent circuit model. The LAPS device and its system were fabricated on the basis of the result of simulation. The fabricated LAPS system showed linear sensitivity (about 56 mV/pH within the range of pH 2 to pH 11. In order to overcome the defect of general urea sensor (especially slow response time), urease immobilized nitrocellulose membrane was attached on the LAPS and resulted in the very fast response time, 0.29 mV/sec, 0.86 mV/sec at urea concentration of $50{\mu}g/ml,\; 500{\mu}g/ml$, respectively. And also in order to measure the uranyl ion, the uranyl ion selective sensing membrane with calix[6]arene derivative was used and its sensitivity was 25mV/concentration decade in the wide uranyl ion concentration range of $10^{-11}M\;to\;10^{-4}M$.