• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.137-142
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• 2023

When designing a SMPS(Switched Mode Power Supply) circuit, a part that is easily overlooked without special consideration is a snubber circuit. However, the performance degradation of the SMPS due to the snubber circuit and the effect on the entire SET cannot be ignored. In addition, a snubber circuit is added to both ends of the switch to protect the device from peak voltage and current during switching and to reduce loss during on/off switching. Therefore, in this paper, for a sufficient understanding of snubber circuits, theoretical analysis and experimental formulas that can be applied by designers during actual circuit design are arranged to promote optimization of snubber circuits.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2201-2203
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• 1999

In this study, we have designed and manufactured not a present elliptic cavity but a circular cavity and we have experimented the operational characteristics. As a result, we obtained the maximum efficiency of 2.1 %. It didn't have any difference compared with elliptic cavity. A circular cavity is much more compact, so far easier to be manufactured than a elliptic cavity. And it can be made at a low cost. At the input energy, parameter $\alpha$, input voltage, and pulse width were in the same condition, we have decided to the optimization of the mesh number of a parallel-mesh circuit which was connected with main power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.21-26
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• 2004

In this paper, a direct method is developed to extact RF equivalent circuit of a packaged BJT without optimization. First, parasitic components of plastic package are removed from measured S-parameters using open and short package patterns. Using package do-embedded S-parameters, a direct and simple method is proposed to extract bonding wire inductance and chip pad capacitance between package lead and chip pad. The small-signal model parameters of internal BJT are next determined by Z and Y-parameter formula derived from RF equivalent circuit. The modeled S-parameters of packaged BJT agree well with measured ones, verifying the accuracy of this new extraction method.

• ETRI Journal
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• v.22 no.1
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• pp.38-46
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• 2000

The extraction of model parameters for embedded passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, a method for optimizing the extraction of these parameters using genetic algorithms is presented. The results of this method are compared with optimization using the Levenberg-Marquardt (LM) algorithm used in the HSPICE circuit modeling tool. A set of integrated resistor structures are fabricated, and their scattering parameters are measured for a range of frequencies from 45 MHz to 5 GHz. Optimal equivalent circuit models for these structures are derived from the s-parameter measurements using each algorithm. Predicted s-parameters for the optimized equivalent circuit are then obtained from HSPICE. The difference between the measured and predicted s-parameters in the frequency range of interest is used as a measure of the accuracy of the two optimization algorithms. It is determined that the LM method is extremely dependent upon the initial starting point of the parameter search and is thus prone to become trapped in local minima. This drawback is alleviated and the accuracy of the parameter values obtained is improved using genetic algorithms.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.137-144
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• 2016

In this paper, we have proposed a circuit complexity optimization ILP algorithm of high-level synthesis system for new multiprocessor design. We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the ILP algorithm. We have achieved is that standard benchmark model for the scheduling of the 5th digital wave filter, it was exactly the same due to the existing datapath scheduling results.

• Journal of Magnetics
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• v.21 no.1
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• pp.65-71
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• 2016

To increase the retaining force, a novel design for a concentric, bi-directional, electromagnetic valve actuator that contains double-layer permanent magnets is presented in this paper. To analyze the retaining-force change caused by the magnets, an equivalent magnetic circuit (EMC) model is established, while the EMC circuit of a double-layer permanent-magnet valve actuator (DLMVA) is also designed. Based on a 3D finite element method (FEM), the calculation model is built for the optimization of the key DLMVA parameters, and the valve-actuator optimization results are adopted for the improvement of the DLMVA design. A prototype actuator is manufactured, and the corresponding test results show that the actuator satisfies the requirements of a high retaining force under a volume limitation; furthermore, the design of the permanent magnets in the DLMVA allow for the attainment of both a high initial output force and a retaining force of more than 100 N.

• Journal of Communications and Networks
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• v.4 no.3
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• pp.230-245
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• 2002

Usually the network-throughput maximization problem for constant-bit-rate (CBR) circuit-switched traffic is posed for a fixed offered load profile. Then choices of routes and of admission control policies are sought to achieve maximum throughput (usually under QoS constraints). However, similarly to the notion of channel “capacity,” it is also of interest to determine the “network capacity;” i.e., for a given network we would like to know the maximum throughput it can deliver (again subject to specified QoS constraints) if the appropriate traffic load is supplied. Thus, in addition to determining routes and admission controls, we would like to specify the vector of offered loads between each source/destination pair that “achieves capacity.” Since the combined problem of choosing all three parameters (i.e., offered load, admission control, and routing) is too complex to address, we consider here only the optimal determination of offered load for given routing and admission control policies. We provide an off-line algorithm, which is based on Lagrangian techniques that perform robustly in this rigorously formulated nonlinear optimization problem with nonlinear constraints. We demonstrate that significant improvement is obtained, as compared with simple uniform loading schemes, and that fairness mechanisms can be incorporated with little loss in overall throughput.

• ETRI Journal
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• v.34 no.6
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• pp.946-949
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• 2012

We present the optimization of a birefringence-enhanced-waveguide (BWG)-based polarization beam splitter (PBS) in a Mach-Zehnder interferometer (MZI) configuration and analyze the structure-dependent or polarization-dependent phase difference, using a delay-line MZI (DL-MZI). We fabricate the DL-MZI using silica-based planar lightwave circuit technology and, using the DL-MZI, demonstrate the ability to optimize a PBS by measuring the birefringence of the BWG and structure-dependent phase offset.