The Journal of the Institute of Internet, Broadcasting and Communication (한국인터넷방송통신학회논문지)

The Institute of Internet, Broadcasting and Communication (한국인터넷방송통신학회)
권호 표지
DOI QR코드

DOI QR Code

A Circuit Complexity Optimization ILP Algorithm of High-level Synthesis System for New Multiprocessor Design

새로운 멀티프로세서 디자인을 위한 상위수준합성 시스템의 회로 복잡도 최적화 ILP 알고리즘

  • Received : 2016.05.20
  • Accepted : 2016.06.10
  • Published : 2016.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we have proposed a circuit complexity optimization ILP algorithm of high-level synthesis system for new multiprocessor design. We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the ILP algorithm. We have achieved is that standard benchmark model for the scheduling of the 5th digital wave filter, it was exactly the same due to the existing datapath scheduling results.

본 논문에서는 새로운 멀티프로세서 디자인을 위한 상위 수준 합성 시스템의 회로 복잡도 최적화 ILP 알고리즘을 제안하였다. 상위수준 합성에서 가장 중요한 연산자의 특성과 데이터패스의 구조를 분석하고, 멀티사이클 연산의 스케줄링 시 가상연산자 개념을 도입함으로써, 멀티사이클 연산을 구현하는 연산자의 유형에 관계없이 공통으로 적용시킬 수 있는 ILP 알고리즘을 이용하여 증명하였다. 기술된 알고리즘의 스케줄링 성능을 평가하기 위하여, 표준벤치마크 모델인 5차 디지털 웨이브필터에 대한 스케줄링을 행한 결과, 기존의 데이터패스 스케줄링 결과와 정확하게 일치함으로서, 제시된 모든 ILP 수식이 정확하게 기술되었음을 알 수 있었다.

Keywords

References

  1. C-H. Lin, "A New Register Transfer Level Synthesis Methodology for Efficient SOC Design", The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), VOL.11 No. 2, April 2011.
  2. Gebotys, Catherine H., and Mohamed I. Elmasry. "Optimal VLSI architectural synthesis: area, performance and testability." Vol. 158. Springer Science & Business Media, 2012.
  3. Gajski, Daniel D., et al. "High-Level Synthesis: Introduction to Chip and System Design." Springer Science & Business Media, 2012.
  4. C.Tseng, D.P.Siewiorek, "Automated Synthesis of Datapath in Digital System", IEEE Tr.CAD, Vol. CAD-5, pp. 379-385, July. 1986.
  5. S.Y.Kung, H.J.Whitehouse, T.Kailath, "VLSI and Modern Signal Processign", Englewood Cliffs, NJ : Prentice Hall, pp. 258-264, 1985.
  6. H.Tricky, "Flamel : A High-Level Hardware Compiler", IEEE Tr. on CAD, pp. 259-269, March. 1987.
  7. P.G.Paulin, et al, "HAL : A Multi-Paradigm Approach to Automatic Data Path Synthesis", Proc.of 23rd DAC, pp. 263-270, June. 1986.
  8. Nemhauser, George L. "Column generation for linear and integer programming." Optimization Stories 20:64, 2012.
  9. Lars Wanhammar, Ya Jun Yu, "Digital Filter Structures and Their Implementation", Academic Press Library in Signal Processing, Vol. 1, pp. 245 -338, 2014. https://doi.org/10.1016/B978-0-12-396502-8.00006-1
  10. Jothi Komal, Akkary Haitham, "Tuning the continual flow pipeline architecture." In: Proceedings of the 27th international ACM conference on International conference on supercomputing. ACM, pp. 243-252. 2013.