• Title/Summary/Keyword: Circuit optimization

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Optimal Design of Micro Actuator Plate Spring Considering Vibration Characteristic (진동 특성을 고려한 마이크로 엑추에이터 판 스프링의 최적설계)

  • 이종진;이호철;유정훈
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2003.11a
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    • pp.220-225
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    • 2003
  • Recent issue of optical actuator is applying to mobile device. It leads actuator to become smaller than conventional type. This paper proposes the design of micro actuator plate spring and analysis of its vibration characteristic. Considering natural frequency of spindle motor, 1st and 2nd eigenfrequency of micro actuator must avoid its natural frequency. First, magnetic circuit is designed by using fine pattern coil and magnetic force is acquired by simulation program. Then, concept design is achieved by topology optimization. From concept design, micro actuator plate spring is embodied through DOE(design of experiment). Finally, considering vibration characteristic simultaneously, optimal plate spring design is determined by RSM(response surface method).

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A Study on Place and Route for FPGA using the Time Driven Optimization

  • Yi Myoung Hee;Yi Jae Young;Tsukiyama Shuji;Laszlo Szirmay
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.70-73
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    • 2004
  • We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

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Converter Utilization Ratio Enhancement in the THD Optimization of Cascaded H-Bridge 7-level Inverters

  • Khamooshi, Reza;Namadmalan, Alireza;Moghani, Javad Shokrollahi
    • Journal of Power Electronics
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    • v.16 no.1
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    • pp.173-181
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    • 2016
  • In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

Successive Max-min Connection-Ratio Preoblem:Routing with Fairness and Efficiency in Circuit Telecommunication Networks (연속적인 최대-최소 연결비율 문제: 회선망에서의 공정성 및 효율성을 보장하는 경로설정)

  • 박구현;우재현
    • Journal of the Korean Operations Research and Management Science Society
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    • v.22 no.2
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    • pp.13-29
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    • 1997
  • This paper considers a new routing problem, successive max-min connection ratio problem (SMCRP), arised in circuit telecommunication networks such as SONET and WDM optical transport network. An optimization model for SMCRP is established based on link-flow formulation. It's first optimization process is an integral version of maximum concurrent flow problem. Integer condition does not give the same connection-ratio of each node-pair at an optimal solution any more. It is also an integral multi-commodity flow problem with fairness restriction. In order to guarantee fairness to every node-pair the minimum of connection ratios to demand is maximized. NP- hardness of SMCRP is proved and a heuristic algorithm with polynomial-time bound is developed for the problem. Augmenting path and rerouting flow are used for the algorithm. The heuristic algorithm is implemented and tested for networks of different sizes. The results are compared with those given by GAMS/OSL, a popular commercial solver for integer programming problem.n among ferrite-pearlite matrix, the increase in spheroidal ratio with increasing fatigue limitation, 90% had the highest, 14.3% increasing more then 70%, distribution range of fatigue.ife was small in same stress level. (2) $\sqrt{area}_{max}$ of graphite can be used to predict fatigue limit of Ductile Cast Iron. The Statistical distribution of extreme values of $\sqrt{area}_{max}$ may be used as a guideline for the control of inclusion size in the steelmaking.

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Computer-Aided Optimal Design of Electronic Systems (전자계산기에 의한 전자기기의 최적 설계방식연구)

  • Kim, Deok-Jin;Park, In-Gap;Kim, Seon-Yeong
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.12 no.6
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    • pp.21-30
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    • 1975
  • A method by which one can optimize the complex responses of electronic circuits has been suggested. represented in the complex forms, the optimization methods presented so far have dealt with real magnitude and phase responses of circuits. Design examples are shown on the optimal designs of an amplifier, filter, operational circuits transmission lines. and a wave-shaping circuit.

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Basic Study on the Optimization of Automotive Battery Post Clamp (자동차용 배터리 포스트 클램프의 최적화에 관한 기초적 연구)

  • Choi, Hae-Kyu;Lee, Evan;Kim, Choon-Sik;Kim, Sei-Hwan;Cho, Jae-Ung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.12
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    • pp.5443-5449
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    • 2011
  • Battery post clamp has the role to fix each of terminals at electric condenser by connecting with the cable of power source. In this study, optimum design was achieved by reducing the material cost and the weight of vehicle with one part of battery post clamp. Stress and displacement were obtained by optimizing with design variables. The advanced model by the design through this study were compared with the original model. These optimum values can be applied usefully with the manufacturing field of battery component.

Energy-Efficient Scheduling with Individual Packet Delay Constraints and Non-Ideal Circuit Power

  • Yinghao, Jin;Jie, Xu;Ling, Qiu
    • Journal of Communications and Networks
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    • v.16 no.1
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    • pp.36-44
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    • 2014
  • Exploiting the energy-delay tradeoff for energy saving is critical for developing green wireless communication systems. In this paper, we investigate the delay-constrained energy-efficient packet transmission. We aim to minimize the energy consumption of multiple randomly arrived packets in an additive white Gaussian noise channel subject to individual packet delay constraints, by taking into account the practical on-off circuit power consumption at the transmitter. First, we consider the offline case, by assuming that the full packet arrival information is known a priori at the transmitter, and formulate the energy minimization problem as a non-convex optimization problem. By exploiting the specific problem structure, we propose an efficient scheduling algorithm to obtain the globally optimal solution. It is shown that the optimal solution consists of two types of scheduling intervals, namely "selected-off" and "always-on" intervals, which correspond to bits-per-joule energy efficiency maximization and "lazy scheduling" rate allocation, respectively. Next, we consider the practical online case where only causal packet arrival information is available. Inspired by the optimal offline solution, we propose a new online scheme. It is shown by simulations that the proposed online scheme has a comparable performance with the optimal offline one and outperforms the design without considering on-off circuit power as well as the other heuristically designed online schemes.

Power Transmission Mechanism and Data Communication of the Dosimeter using Contactless Powerless Transmission (선량계의 무선전력 전송 메카니즘과 데이터 통신 시스템 구현)

  • Lee, Seung-Min;Chung, Sung-In;Lee, Heung-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.4
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    • pp.814-819
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    • 2010
  • This study proposes the antenna circuit design for the transmitting wireless power, the development of the RF non-contact type Dosimeter. That is, the study designed the optimization and numerical analysis of the antenna circuit for the antenna design of 13.56MHz over the frequency bands for transmitting wireless power. We studied the needed items in the existing RF type Dosimeter with battery to implement the wireless power non-contact Dosimeter within the battery. We compared to the real measurement value as calculating the value of the inductance and capacitance through the numerical analysis for the antenna LC resonance using the theory of the electromagnetic induction method. This method to drive low power is designed to simplify the circuit and to improve the efficiency of the rectifier. We convince our research contributes not only to understand the simplified circuit and miniaturization, but also to help the design and application technology of the wireless power transmit system which is received power supply with wireless.

A SPICE-based 3-dimensional circuit model for Light-Emitting Diode (SPICE 기반의 발광 다이오드 3차원 회로 모델)

  • Eom, Hae-Yong;Yu, Soon-Jae;Seo, Jong-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.7-12
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    • 2007
  • A SPICE-based 3-dimensional circuit model of LED(Light-Emitting Diode) was developed for the design optimization and analysis of high-brightness LEDs. An LED is represented as an array of pixel LEDs with small preassigned areas, and each of the pixel LEDs is composed of circuit networks representing the thin-film layers(n-metal, n- and p-type semiconductor layers, and p-metal), ohmic contacts, and pn-junctions. Each of the thin-film layers and contact resistances is modeled by a resistance network, and the pn-junction is modeled by a conventional pn-junction diode. It has been found that the simulation results using the model and the corresponding parameters precisely fit the measured LED characteristics.

A Novel Zero-Crossing Compensation Scheme for Fixed Off-Time Controlled High Power Factor AC-DC LED Drivers

  • Chang, Changyuan;Sun, Hailong;Zhu, Wenwen;Chen, Yao;Wang, Chenhao
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1661-1668
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    • 2016
  • A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.