• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• ETRI Journal
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• 제39권5호
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• 한국인터넷방송통신학회논문지
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• 제23권4호
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• pp.137-142
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• 2023

SMPS(Switched Mode Power Supply, 전력공급장치) 회로설계 시 특별한 고찰 없이 지나치기 쉬운 부분이 스너버(snubber) 회로이다. 그러나 스너버(snubber) 회로에 따른 SMPS의 성능저하 및 SET 전체에 미치는 영향은 결코 무시할 수 없다. 또한 스위칭시 피크치 전압과 전류로부터 소자를 보호하고 on/off 스위칭시 손실을 줄여주기 위하여 스위치 양단에 스너버(snubber) 회로를 부가해준다. 따라서 본 논문에서는 스너버(snubber) 회로에 대한 충분한 이해를 위해 이론적 해석 및 실제 회로설계 때 설계자가 응용할 수 있는 실험식을 정리하여, 스너버(snubber) 회로의 최적화를 도모하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2201-2203
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• 1999

In this study, we have designed and manufactured not a present elliptic cavity but a circular cavity and we have experimented the operational characteristics. As a result, we obtained the maximum efficiency of 2.1 %. It didn't have any difference compared with elliptic cavity. A circular cavity is much more compact, so far easier to be manufactured than a elliptic cavity. And it can be made at a low cost. At the input energy, parameter $\alpha$, input voltage, and pulse width were in the same condition, we have decided to the optimization of the mesh number of a parallel-mesh circuit which was connected with main power supply.

• 대한전자공학회논문지SD
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• 제41권12호
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• pp.21-26
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• 2004

본 논문에서는 package된 BJT의 RF 등가회로 모델을 optimization과정 없이 직접 추출하는 방법을 개발하였다. 먼저, open 과 short package 구조를 사용하여 plastic package의 기생성분을 측정된 S-파라미터로부터 정확히 제거하였다. 이와 같이 package do-embedding된 S-파라미터로부터 package lead와 chip pad 사이의 bonding wire 인덕턴스와 chip pad 캐패시턴스를 직접 추출하는 간단한 방법을 구축하였다. 그 후에 내부 BJT소자의 소신호 모델변수들은 RF 등가회로로부터 유도된 Z나 Y-파라미터 방정식을 이용하여 결정하였다. 이 방법으로 모델화된 packaged BJT의 S-파라미터는 측정 데이터와 아주 잘 일치하였으며 이는 새로운 추출방법의 정확성을 증명한다.

• ETRI Journal
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• 제22권1호
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• pp.38-46
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• 2000

The extraction of model parameters for embedded passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, a method for optimizing the extraction of these parameters using genetic algorithms is presented. The results of this method are compared with optimization using the Levenberg-Marquardt (LM) algorithm used in the HSPICE circuit modeling tool. A set of integrated resistor structures are fabricated, and their scattering parameters are measured for a range of frequencies from 45 MHz to 5 GHz. Optimal equivalent circuit models for these structures are derived from the s-parameter measurements using each algorithm. Predicted s-parameters for the optimized equivalent circuit are then obtained from HSPICE. The difference between the measured and predicted s-parameters in the frequency range of interest is used as a measure of the accuracy of the two optimization algorithms. It is determined that the LM method is extremely dependent upon the initial starting point of the parameter search and is thus prone to become trapped in local minima. This drawback is alleviated and the accuracy of the parameter values obtained is improved using genetic algorithms.

• 한국인터넷방송통신학회논문지
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• 제16권3호
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• pp.137-144
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• 2016

본 논문에서는 새로운 멀티프로세서 디자인을 위한 상위 수준 합성 시스템의 회로 복잡도 최적화 ILP 알고리즘을 제안하였다. 상위수준 합성에서 가장 중요한 연산자의 특성과 데이터패스의 구조를 분석하고, 멀티사이클 연산의 스케줄링 시 가상연산자 개념을 도입함으로써, 멀티사이클 연산을 구현하는 연산자의 유형에 관계없이 공통으로 적용시킬 수 있는 ILP 알고리즘을 이용하여 증명하였다. 기술된 알고리즘의 스케줄링 성능을 평가하기 위하여, 표준벤치마크 모델인 5차 디지털 웨이브필터에 대한 스케줄링을 행한 결과, 기존의 데이터패스 스케줄링 결과와 정확하게 일치함으로서, 제시된 모든 ILP 수식이 정확하게 기술되었음을 알 수 있었다.

• Journal of Magnetics
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• 제21권1호
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• pp.65-71
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• 2016

To increase the retaining force, a novel design for a concentric, bi-directional, electromagnetic valve actuator that contains double-layer permanent magnets is presented in this paper. To analyze the retaining-force change caused by the magnets, an equivalent magnetic circuit (EMC) model is established, while the EMC circuit of a double-layer permanent-magnet valve actuator (DLMVA) is also designed. Based on a 3D finite element method (FEM), the calculation model is built for the optimization of the key DLMVA parameters, and the valve-actuator optimization results are adopted for the improvement of the DLMVA design. A prototype actuator is manufactured, and the corresponding test results show that the actuator satisfies the requirements of a high retaining force under a volume limitation; furthermore, the design of the permanent magnets in the DLMVA allow for the attainment of both a high initial output force and a retaining force of more than 100 N.

• Journal of Communications and Networks
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• 제4권3호
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• pp.230-245
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• 2002

Usually the network-throughput maximization problem for constant-bit-rate (CBR) circuit-switched traffic is posed for a fixed offered load profile. Then choices of routes and of admission control policies are sought to achieve maximum throughput (usually under QoS constraints). However, similarly to the notion of channel “capacity,” it is also of interest to determine the “network capacity;” i.e., for a given network we would like to know the maximum throughput it can deliver (again subject to specified QoS constraints) if the appropriate traffic load is supplied. Thus, in addition to determining routes and admission controls, we would like to specify the vector of offered loads between each source/destination pair that “achieves capacity.” Since the combined problem of choosing all three parameters (i.e., offered load, admission control, and routing) is too complex to address, we consider here only the optimal determination of offered load for given routing and admission control policies. We provide an off-line algorithm, which is based on Lagrangian techniques that perform robustly in this rigorously formulated nonlinear optimization problem with nonlinear constraints. We demonstrate that significant improvement is obtained, as compared with simple uniform loading schemes, and that fairness mechanisms can be incorporated with little loss in overall throughput.

• ETRI Journal
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• 제34권6호
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• pp.946-949
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• 2012

We present the optimization of a birefringence-enhanced-waveguide (BWG)-based polarization beam splitter (PBS) in a Mach-Zehnder interferometer (MZI) configuration and analyze the structure-dependent or polarization-dependent phase difference, using a delay-line MZI (DL-MZI). We fabricate the DL-MZI using silica-based planar lightwave circuit technology and, using the DL-MZI, demonstrate the ability to optimize a PBS by measuring the birefringence of the BWG and structure-dependent phase offset.