• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.196-200
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• 2005

A 40 channel arrayed-waveguide grating (AWG) filter operating in C-band and L-band wavelength regions has been fabricated using PLC (Planar Lightwave Circuit) processes with 0.75 refractive index difference. Its design was optimized for matching the center wavelength with the ITU-recommended wavelength. The characteristics of the fabricated C-band AWG are as follows; average insertion loss < 2.5 dB, polarization-dependent loss < 0.3 dB, non-adjacent crosstalk >35dB, and the loss uniformity of 0.8 dB. In the L-band AWG, wavelength accuracy is below 0.02nm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.9
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• pp.59-64
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• 2015

IEC is an international standards which are used in many countries with Europe as the center. IEC standard is introduced in Korea according to WTO/TBT agreements, however until now there are no buildings in Korea which are designed applying IEC standard. Therefore, KEA(Korea Electric Association) is scheduled to construct Korean low voltage electrical installation integration test site which is designed applying IEC standard. In this paper, before being under construction of Korean low voltage electrical installation integration test site, power substation is modeled based on real design parameters and method to select circuit breakers and cables is presented applying IEC standard in the modeled power substation. EMTP(ElctroMagnetic Transient Program) is used for simulation program. EMTP which is power system analysis program is easy to model power system and power substation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.31-39
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• 2001

In this paper, we proposed a new pixel circuit of the CMOS image sensor for high dynamic range operation, which is based on a multiple sampling scheme and a conditional reset circuit. To expand the pixel dynamic range, the output is multiple-sampled in the integration time. In each sampling, the pixel output is compared with a reference voltage, and the result of comparison may activate the conditional reset circuit. The times of conditional reset, N, during the integration will contribute to the increase of the dynamic range by the times of N. The test chip was fabricated with 0.65-${\mu}m$ CMOS technology (2-P, 2-M).

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.2
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• pp.107-113
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• 2012

This paper proposes a PDS(Power Transfer Display separation) method for AC-PDP. The proposed PDS method can transfer power and perform an energy recovery by a power conversion circuit operates differently depending on the time. As a result, it uses less of components than conventional PDP power supply and sustain circuit use. Moreover, the manufacturing process can be streamlined. Therefore, the proposed method is suitable for low cost PDP module. To confirm the operation, validity and features of the proposed PDS method, experimental results from a prototype for 42-in diagonal PDP are presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.8
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• pp.1180-1185
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• 2015

This paper describes the accurate inductance measurement of a switched reluctance motor (SRM). Conventionally, the inductance of the SRM is measured using the equivalent circuit of a stator phase or time constant of exponential current transient. This paper presents an effective method to measure the SRM inductance accurately and rapidly using automated voltage integration. The proposed method is validated experimentally by comparison with the existing equivalent circuit method (ECM) and the FEA(finite element analysis) simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Progress in Superconductivity
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• v.5 no.1
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• pp.1-4
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• 2003

A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.