• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.25-32
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• 2006

In this paper, we propose a fast correlation attack on the shrinking and self-shrinking generator. This attack is an improved algorithm or the fast correlation attack by Zhang et al. at CT-RSA 2005. For the shrinking generator, we recover the initial state of generating LFSR whose length is 61 with $2^{15.43}$ keystream bits, the computational complexity of $2^{56.3314}$ and success probability 99.9%. We also recover the initial state of generating LFSR whose length is $2^{40}$ of the self-shrinking generator with $2^{45.89}$ keystream bits, the computational complexity of $2^{112.424}$ and success probability 99.9%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.6
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• pp.3-13
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• 2010

Differential Fault Analysis (DFA) is widely known for one of the most efficient method analyzing block cipher. In this paper, we propose a new type of DFA on DES (Data Encryption Standard). DFA on DES was first introduced by Biham and Shamir, then Rivain recently introduced DFA on DES middle rounds (9-12 round). However previous attacks on DES can only be applied to the encryption process. Meanwhile, we first propose the DFA on DES key-schedule. In this paper, we proposed a more efficient DFA on DES key schedule with random fault. The proposed DFA method retrieves the key using a more practical fault model and requires fewer faults than the previous DFA on DES.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.1051-1077
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• 2021

The secure communication of information is a major concern over the internet. The information must be protected before transmitting over a communication channel to avoid security violations. In this paper, a new hybrid method called compressed encrypted data embedding (CEDE) is proposed. In CEDE, the secret information is first compressed with Lempel Ziv Welch (LZW) compression algorithm. Then, the compressed secret information is encrypted using the Advanced Encryption Standard (AES) symmetric block cipher. In the last step, the encrypted information is embedded into an image of size 512 × 512 pixels by using image steganography. In the steganographic technique, the compressed and encrypted secret data bits are divided into pairs of two bits and pixels of the cover image are also arranged in four pairs. The four pairs of secret data are compared with the respective four pairs of each cover pixel which leads to sixteen possibilities of matching in between secret data pairs and pairs of cover pixels. The least significant bits (LSBs) of current and imminent pixels are modified according to the matching case number. The proposed technique provides double-folded security and the results show that stego image carries a high capacity of secret data with adequate peak signal to noise ratio (PSNR) and lower mean square error (MSE) when compared with existing methods in the literature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.56-64
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• 2012

A smart grid is the next generation power grid which combines the existing power grid with information technology, so an energy efficient power grid can be provided. In this paper, in order to build an efficient smart grid an AMI system, which gears with the existing home network and provides an user friendly management function, is proposed. The proposed AMI system, which is based on an extended home network, consists of various functional units; smart meters, communication modules, home gateway, security modules, meter data management modules (MDMM), electric power application modules and so on. The proposed home network system, which can reduce electric power consumption and transmit data more effectively, is designed by using IEEE 802.15.4. The extended home gateway can exchange energy consumption information with the outside management system via web services. The proposed AMI system is designed to enable two-way communication between the home gateway and MDMM via the Internet. The AES(Advanced Encryption Standard) algorithm, which is a symmetric block cipher algorithm, is used to ensure secure information exchange. Even though the results in this study could be limited to our experimental environment, the result of the simulation test shows that the proposed system reduces electric power consumption by 4~42% on average compared to the case of using no control.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1301-1308
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• 2018

90/150 CA which are used as key generators of the cipher system have more randomness than LFSRs, but synthesis methods of 90/150 CA are difficult. Therefore, 90/150 CA synthesis methods have been studied by many researchers. In order to synthesize a suitable CA, the analysis of the characteristic polynomial of 90/150 CA should be preceded. In general, the characteristic of polynomial ${\Delta}_n$ of n cell 90/150 CA is obtained by using ${\Delta}_{n-1}$ and ${\Delta}_{n-2}$. Choi et al. analyzed $H_{2^n}(x)$ and $H_{2^n-1}(x)$, where $H_k(x)$ is the characteristic polynomial of k cell 90/150 CA with state transition rule <$10{\cdots}0$>. In this paper, we propose an efficient method to obtain $H_n(x)$ from $H_{n-1}(x)$ and an efficient algorithm to obtain $H_{2^n+i}(x)$ and $H_{2^n-i}(x)$ ($1{\leq}i{\leq}2^{n-1}$) from $H_{2^n}(x)$ by using this method.