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http://dx.doi.org/10.13089/JKIISC.2006.16.6.15

Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer  

Ryu, Gwon-Ho (National Security Research Institute(NSRI))
Koo, Bon-Seok (National Security Research Institute(NSRI))
Yang, Sang-Woon (National Security Research Institute(NSRI))
Chang, Tae-Joo (National Security Research Institute(NSRI))
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.16, no.6, 2006 , pp. 15-24 More about this Journal
Abstract
Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.
Keywords
ARIA processor; Diffusion; Light Weight; gate count;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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