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Low Power Implementation of Integrated Cryptographic Engine for Smart Cards  

Kim, Yong-Hee (Department of Electronics and Communications Engineering, Kwangwoon University)
Jeong, Yong-Jin (Department of Electronics and Communications Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.6, 2008 , pp. 80-88 More about this Journal
Abstract
In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.
Keywords
low power; small area; smart card; clock gating; cryptography;
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