• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2015년도 제52차 하계학술대회논문집 23권2호
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• pp.73-74
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• 2015

본 논문에서는 SSL/TLS에서 발생할 수 있는 cipher suite rollback 공격 탐지를 위해 선택된 알고리즘을 리스트로 검증하는 방법을 제안한다. 제안 기법은 SSL/TLS의 핸드셰이크 단계에서 이루어진다. 클라이언트 기기가 암호화 알고리즘의 순위를 리스트로 만들고 핸드셰이크가 끝난 후에 선택된 알고리즘의 순위를 비교해서 해당 기기에 대한 공격을 의심하도록 한다. 그러므로 우리의 제안 기법은 cipher suite rollback 공격 탐지를 향상시키고 안전한 메시지 통신을 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.165-168
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• 2000

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

• 정보보호학회논문지
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• 제29권4호
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• pp.709-718
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• 2019

CHAM은 자원이 제한된 환경에 적합하도록 설계된 경량 블록 암호 알고리즘으로서 안전성과 연산 성능면에서 우수한 특성을 보인다. 그러나 이 알고리즘도 부채널 공격에 대한 취약성을 그대로 내재하고 있기 때문에 마스킹 기법과 같은 대응 기법이 적용되어야 한다. 본 논문에서는 32비트 마이크로프로세서 Cortex-M3 플랫폼에서 부채널 공격에 대응하는 마스킹 기법이 적용된 CHAM 알고리즘을 구현하고 성능을 비교 분석한다. 또한, CHAM 알고리즘이 라운드 수가 많아 연산 효율이 감소되는 점을 고려하여 축소 마스킹 기법을 적용하여 성능을 평가하였다. 축소 라운드 마스킹이 적용된 CHAM-128/128은 구현 결과 마스킹이 없는 경우에 비해 약 4배 정도의 추가 연산이 필요함을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권5호
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• pp.1611-1633
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• 2022

At EUROCRYPT 2019, a new block cipher algorithm called BISON was proposed by Canteaut et al. which uses a novel structure named as Whitened Swap-Or-Not (WSN). Unlike the traditional wide trail strategy, the differential and linear properties of this algorithm can be easily determined. However, the encryption speed of the BISON algorithm is quite low due to a large number of iterative rounds needed to ensure certain security margins. Commonly, denoting by n is the data block length, this design requires 3n encryption rounds. Moreover, the block size n of BISON is always odd, which is not convenient for operations performed on a byte level. In order to overcome these issues, we propose a new block cipher, named DBISON, which more efficiently employs the ideas of double layers typical to the BISON-like construction. More precisely, DBISON divides the input into two parts of size n/2 bits and performs the round computations in parallel, which leads to an increased encryption speed. In particular, the data block length n of DBISON can be even, which gives certain additional implementation benefits over BISON. Furthermore, the resistance of DBISON against differential and linear attacks is also investigated. It is shown the maximal differential probability (MDP) is 1/2^n-1 for n encryption rounds and that the maximal linear probability (MLP) is strictly less than 1/2^n-1 when (n/2+3) iterative encryption rounds are used. These estimates are very close to the ideal values when n is close to 256.

• 정보보호학회지
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• 제4권1호
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• pp.76-87
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• 1994

지난호에는 IS 10116 : n비트 블럭 암호 알고리즘의 운영모드(Modes of operation for a 64-bit blick cipher algorithm)를 소개하였다. 이번 호에는 보다 n=64의 경우에 한정되어 제한적이기는 하지만 훨씬 먼저인 1987년에 만들어져 사용 되어오고 있으며 1992년 정보보안 국제총회에서 이미 많은 제품이 IS 8372를 근거로 만들어져 있기 때문이라는 이유로 다시 5년간 국제표준으로서 수명의 연장을 받은 IS 8372를 소개한다.

• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• 정보보호학회논문지
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• 제12권2호
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• 한국컴퓨터산업학회논문지
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• 제4권4호
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• pp.523-532
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• 2003

본 논문에서는 확장된 Feistel 구조를 갖는 128-비트 블록 암호알고리즘 Lambda를 설계하고, 차분공격(differential cryptanalysis)과 선형공격(linear cryptanalysis)을 통해 안전성을 분석하였다. Lambda는 2-라운드 만에 완전 확산(diffusion)이 일어나도록 설계되었다. 이러한 우수한 확산효과로 인해 8-라운드 차분 특성이 구성될 확률은 $2^{-128}$로, 선형특성이 구성될 확률은 $2^{-192}$로 분석되었다. 결과적으로 Lambda는 128-비트 비밀키를 적용하였을 경우 8-라운드 이상이면 차분공격이나 선형공격이 전사(exhaustive)공격 방법보다 효율성이 떨어지는 것으로 분석되었다.

• International Journal of Internet, Broadcasting and Communication
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• 제8권1호
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• pp.42-52
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• 2016

In this paper, we propose the 16-bits optimization design of the ARIA block-cipher algorithm for embedded systems with 16-bits processors. The proposed design adopts 16-bits XOR operations and rotated shift operations as many as possible. Also, the proposed design extends 8-bits array variables into 16-bits array variables for faster chained matrix multiplication. In evaluation experiments, our design is compared to the previous 32-bits optimized design and 8-bits optimized design. Our 16-bits optimized design yields about 20% faster execution speed and about 28% smaller footprint than 32-bits optimized code. Also, our design yields about 91% faster execution speed with larger footprint than 8-bits optimized code.

• Journal of Ubiquitous Convergence Technology
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• 제2권1호
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.