Journal of information and communication convergence engineering

  • 제3권4호
  • /
  • Pages.201-204
  • /
  • 2005
  • /
  • 2234-8255(pISSN)
  • /
  • 2234-8883(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
권호 표지

High-speed Hardware Design for the Twofish Encryption Algorithm

  • Youn Choong-Mo (School of Information Technology, Seoil College) ;
  • Lee Beom-Geun (Department of Electronic Engineering, Kyunghee University)
  • 발행 : 2005.12.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

키워드

참고문헌

  1. Feistel, 'Cryptography and Computer Privacy', Scientific American, May 1973
  2. Pawel Chodowiec, Kris Gaj, 'Implementation of the Twofish Cipher Using FPGA Devices', Technical Report, George Mason University, 1999
  3. Brace Schneier, 'Applied Cryptography', John Wiley & Sons Inc., 1996
  4. Feistel, 'Cryptography and ComputerPrivacy', Scientific American, 1973
  5. C. Paar, 'Optimized Arithmetic for Reed-Solomon Encoders', 1997 IEEE International Symposium on Information Theory, 1997 https://doi.org/10.1109/ISIT.1997.613165
  6. C. Paar, M. Rosner, 'Comparison of Arithmetic Architectures for Reed-Solomon Decoders in Reconfigurable Hardware', Fifth Annual IEEE Symposium on Field-Programmable Custom Computing Machines FCCM '97. 1997. USA https://doi.org/10.1109/FPGA.1997.624622