• Journal of Korea Society of Industrial Information Systems
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• v.11 no.2
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• pp.98-102
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• 2006

Recent development of Information Technology, the ubiquitous computing environment is on the rise. At the same time, RFID technology and its related applications are actively investigated. In this paper, a portable merchandise information providing system using cheap wireless transmission module is developed in order to overcome the mobility limitation of the wired RFID system. The TRF6901 chipset of 900MHz band from TI is used for the wireless transmission module and the MPS430F149 is used for the MPU. It is expected that the developed system can be applied to numerous innovative wireless applications such as library circulation desk for lending service and automated door system for entrance control.

• ETRI Journal
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• v.42 no.4
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.45-53
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• 1999

A pre amplifier, a limiting amplifier, and a decision IC chipset for 10Gbit/s optical receiver was implemented with AIGaAs/GaAs HBT(Heterojunction Bipolar Transistor) technology. The HBT allows a cutoff frequency of 55GHz and a maximum oscillation of 45GHz. An optical receiver front-end was implemented with the fabricated pre amplifier IC and a PIN photodiode. It showed 46dB$\Omega$, gain and $f_{3db}$ of 12.3GHz. The limiting amplifier Ie showed 27dB small signal gain, $f_{3db}$ of 1O.6GHz, and the output is limited to 900mVp-p from 20mVp-p input voltage. The decision circuit IC showed 300-degree phase margin and input voltage sensitivity of 47mVp-p at 1OGbit/s.

• The KIPS Transactions:PartC
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• v.11C no.7 s.96
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• pp.951-958
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• 2004

Nowadays NGN is developed for supporting the e-Commerce, Internet trading, e-Government, e-mail, virtual-life and multimedia. Internet gives us the benefit of remote access to the information but causes the attacks that can break server and modify information. Since 2000 Nimda, Code Red Virus and DSoS attacks are spreaded in Internet. This attack programs make tremendous traffic packets on the Internet. In this paper, we designed and developed the Bandwidth Controller in the gateway systems against the bandwidth saturation attacks. This Bandwidth con-troller is implemented in hardware chipset(FPGA) Virtex II Pro which is produced by Xilinx and acts as a policing function. We reference the TBF(Token Bucket Filter) in Linux Kernel 2.4 and implemented this function in HDL(Hardware Description Language) Verilog. This HDL code is synthesized in hardware chipset and performs the gigabit traffic in real time. This policing function can throttle the traffic at the rate of band width controlling policy in bps speed.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.5
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• pp.13-25
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• 2008

This study analyzed errors of data received from GPS which showed different reception characteristics based on chipset at poor reception area. The digital map made from National Police Agency shows 4% errors of length on the average. The comparison of three different algorithms - Average Spot Speed, Cumulative Travel Length from GPS with Actual Travel Time, Travel Length from Digital Map with Actual Travel Time have been conducted to find significant difference estimating travel time from GPS Data. The algorithm to estimate travel time from travel length and travel time showed the most reliable results from the others.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.109-112
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• 2000

The satellite communications are expected to play an important role to provide broadband multimedia services in the 21st century. According to this requirements, this paper describes the design and implementation of ATM-based high speed satellite modem ASIC chipset. The ASIC chip consists of three main parts, CODEC, Modulator and Demodulator. It supports burst and continuous mode operation with TDMA frame consisted of Reference bursts, Inbound burst, and Traffic burst. The maximum transmission rate is OC-3 (155Mbps) and the maximum operating clock speed is 220MHz. This ASIC chip was implemented with 0.25um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1185-1194
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• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• ETRI Journal
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• v.31 no.3
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• pp.247-253
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• 2009

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.63-72
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• 2004

The supply voltage has been drop rapidly and the total length of the wire increased exponentially in the nanometer SoC design environment. The ideal supply voltage was dropped sharply by the resistance and parasitic devices which stayed on the kilometers-long wire length. Even worse, it could severely affect the functional behavior of the block of the design. To analyze the effects of the long wire of the SoC while maintaining the accuracy, the modeling of the current and the RC conversion of the parasitic techniques are researched and applied. By these modeling and conversion, the multi-million gates HDTV Chipset can be analyzed within a day. The benchmark analysis of the HDTV SoC showed the superiority to the conventional methods in performance and accuracy.