전기전자학회논문지 (Journal of IKEEE)

  • 제8권1호
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  • Pages.63-72
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  • 2004
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지

효율적 전류모델을 이용한 고속의 전압 강하와 동적 파워 소모의 분석 기술

Prediction of Dynamic Power Consumption and IR Drop Analysis by efficient current modeling

  • 발행 : 2004.07.01
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초록

The supply voltage has been drop rapidly and the total length of the wire increased exponentially in the nanometer SoC design environment. The ideal supply voltage was dropped sharply by the resistance and parasitic devices which stayed on the kilometers-long wire length. Even worse, it could severely affect the functional behavior of the block of the design. To analyze the effects of the long wire of the SoC while maintaining the accuracy, the modeling of the current and the RC conversion of the parasitic techniques are researched and applied. By these modeling and conversion, the multi-million gates HDTV Chipset can be analyzed within a day. The benchmark analysis of the HDTV SoC showed the superiority to the conventional methods in performance and accuracy.

키워드

참고문헌

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