• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 1999.12a
• /
• pp.155-162
• /
• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• Proceedings of the KWS Conference
• /
• 2006.05a
• /
• pp.16-17
• /
• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.20 no.5
• /
• pp.559-563
• /
• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.23 no.6
• /
• pp.609-617
• /
• 2014

We have studied a chip-on-board LED lighting optical system for various luminous-intensity-distribution angles of the LED. An optical system that can accept different LEDs was made to reduce the systems's weight and size as we selected the chip-on-board LED, which is easy to apply to optical systems, unlike existing package-on-board LEDs. The luminous-intensity-distribution angles were $45^{\circ}$, $60^{\circ}$, $90^{\circ}$, and $120^{\circ}$. We researched these four types of optical systems. The $45^{\circ}$ and $60^{\circ}$ units were developed into reflectors, and the $90^{\circ}$ and $120^{\circ}$ units, into lenses. We checked the performance of the designed optical system through simulation and made a mock-up. Then we made a prototype of the chip-on-board LED high bay for use with the mock-up. After measuring its performance, we tested the luminous-intensity-distribution angles and compared them with simulation data. The resulting prototype was developed considering brightness, light uniformity, age, and economics which are suitable for a factory environment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.4
• /
• pp.1-10
• /
• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1994.06a
• /
• pp.957-962
• /
• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• ETRI Journal
• /
• v.33 no.3
• /
• pp.335-343
• /
• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• Journal of the Korean Wood Science and Technology
• /
• v.16 no.2
• /
• pp.1-41
• /
• 1988

For the purpose of utilizing the sawdust having poor combining properties as board raw material and resulting in dimensional instability of board, polypropylene chip (abbreviated below as PP chip) or oriented PP thread was combined with sawdust particle from white meranti(Shorea sp.). The PP chip was prepared from PP thread in length of 0.25, 0.5, 1.0 and 1.5 cm for conventional blending application. Thereafter, the PP chip cut as above was combined with the sawdust particle by 3, 6, 9, 12 and 15% on the weight basis of board. Oriented PP threads were aligned with spacing of 0.5, 1.0 and 1.5cm along transverse direction of board. The physical and mechanical properties on one, two and three layer boards manufactured with the above combining conditions were investigated. The conclusions obtained at this study were summarized as follows: 1. In thickness swelling, all one layer boards combined with PP chips showed lower values than control sawdustboard, and gradually clear decreasing tendendy with the increase of PP chip composition. Two layer board showed higher swelling value than one layer board, but the majority of boards lower values than control sawdustboard. All three layer boards showed lower swelling values than control sawdustboard. 2. In the PP chip and oriented thread combining board, the swelling values of boards combining 0.5cm spacing oriented thread with 1.0 or 1.5cm long PP chip in 12 and 15% by board weight were much lower than the lowest of one or three layer. 3. In specific gravity of 0.51, modulus of rupture of one layer board combined with 3% PP chip showed higher value than control sawdustboard. However, moduli of rupture of the boards with every PP chip composition did not exceed 80kgf/cm2, the low limit value of type 100 board, Korean Industrial Standard KS F 3104 Particleboards. Moduli of rupture of 6%, 1.5cm-long and 3% PP chip combined boards in specific gravity of 0.63 as well as PP chip combined board in specific gravity of 0.72 exceeded 80kgf/$cm^2$ on KS F 3104. Two layer boards combined with every PI' chip composition showed lower values than control sawdustboard and one layer board. Three layer boards combined with.1.5cm long PP chip in 3, 6 and 9% combination level showed higher values than control sawdustboard, and exceeded 80kgf/$cm^2$ on KS F 3104. 4. In modulus of rupture of PP thread oriented sawdustboard, 0.5cm spacing oriented board showed the highest value, and 1.0 and 1.5cm spacing oriented boards lower values than the 0.5cm. However, all PP thread oriented sawdustboards showed higher values than control saw-dustboard. 5. Moduli of rupture in the majority of PP chip and oriented thread combining boards were higher than 80kgf/$cm^2$ on KS F 3104. Moduli of rupture in the boards combining longer PP chip with narrower 0.5cm spacing oriented thread showed high values. In accordance with the spacing increase of oriented thread, moduli of rupture in the PP chip and oriented thread combining boards showed increasing tendency compared with oriented sawdustboard. 6. Moduli of elasticity in one, two and three layer boards were lower than those of control sawdustboard, however, moduli of elasticity of oriented sawdustboards with 0.5, 1.0 and 1.5cm spacing increased 20, 18 and 10% compared with control sawdustboard, respectively. 7. Moduli of elasticity in the majority of PP chip and oriented thread combining boards in 0.5, 1.0 and 1.5cm oriented spacing showed much higher values than control sawdustboard. On the whole, moduli of elasticity in the oriented boards combined with 9% or less combination level and 0.5cm or more length of PP chip showed higher values than oriented sawdustboard. The increasing effect on modulus of elasticity was shown by the PP chip composition in oriented board with narrow spacing. 8. Internal bond strengths of all one layer PP chip combined boards showed lower values than control sawdust board, however, the PP chip combined boards in specific gravity of 0.63 and 0.72 exceeded 1.5kgf/$cm^2$, the low limit value of type 100 board and 3kgf/$cm^2$, type 200 board on KS F 3104, respectively. And also most of all two, three layer-and oriented boards exceeded 3kgf/$cm^2$ on KS F. 9. In general, screw holding strength of one layer board combined with PP chip showed lower value than control sawdustboard, however, that of two or three layer board combined with PP chip did no decreased tendency, and even screw holding strength with the increase of PP chip composition. In the PP chip and oriented PP thread combining boards, most of the boards showed higher values than control sawdustboard in 9% or less PP chip composition.

• Journal of the Semiconductor & Display Technology
• /
• v.1 no.1
• /
• pp.29-33
• /
• 2002

In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.21 no.2
• /
• pp.225-231
• /
• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.