• ETRI Journal
• /
• v.38 no.5
• /
• pp.981-987
• /
• 2016

We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

• Journal of information and communication convergence engineering
• /
• v.6 no.4
• /
• pp.376-382
• /
• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.12
• /
• pp.1021-1026
• /
• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.146-153
• /
• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.36T no.4
• /
• pp.115-122
• /
• 1999

The Y2K bug, what is called "millennium bug" or "2000 year bug", take place because the year after 2000 year is not recognize as the year marking method of the computer designed for take up two-digit number. This takes place because the RTC chip architecture of PC can not change the century information to the operating together with date. In this paper, we make an analysis about Y2K hardware bug of RTC in the IBM compatible PC, and make a Y2K compensation board in order to solve Y2K hardware bug. And the test results by various Y2K diagnosis program is bug before put in Y2K compensation board, but is not bug after put in Y2K compensation board. Therefore, we suggest a solution method for Y2K hardware bug of RTC in the IBM compatible PC.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.4
• /
• pp.15-22
• /
• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.2266-2270
• /
• 2005

In this paper, an internet based control application for dynamical systems is implemented. This implementation is maily targeted for the part of advanced control education. Intelligent control algorithms are implemented in a PC so that a client can remotely access the PC to control a dynamical system through the internet. Neural network is used as an on-line intelligent controller. To have on-line learning and control capability, the reference compensation technique is implemented as intelligent control hardware of combining a DSP board and an FPGA chip. GUIs for a user are also developed for the user's convenience. Actual experiments of motion control of a DC motor have been conducted to show the performance of the intelligent control though the internet and the feasibility of advanced control education.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.1
• /
• pp.7-13
• /
• 2011

According to increasing of data transfer rate, printed circuit board (PCB) is required improvement of transmission speed. Optical PCB and its packaging technology can be one of the solutions that overcome the limitations of conventional electrical PCB. The data transmission capacity will be increased 10 Tbps at 2015. To this end, studies on various OPCB technologies are being conducted. For cost-effective and high- performance OPCB, studies of optical coupling by polymer replication process are conducted. In this work, optical waveguide and optical fiber array block were sequentially fabricated by polymer pattern replication method. Using this method we successfully demonstrate low loss optical fiber coupling between optical waveguide and optical fiber arrays. And researches on flip chip bonding process and using electro-optic connectors for packaging are conducted.

• Bulletin of the Korean Chemical Society
• /
• v.31 no.11
• /
• pp.3084-3092
• /
• 2010

This paper describes the development of an automated, hand-held sensor for the fast assessment of seafood freshness. The sensor developed here combined: an array-based chemical sensor, composed of incrementally different conducting polymer elements deposited on a small chip; a highly sensitive, custom-made electronics for the detection of very small signal changes; precise temperature control of the sensor chamber; and an on-board microcontroller for data collection, storage, automation, and analysis. The instrument was used to successfully test seafood samples with different degree of freshness and spoilage. A linear relationship between microbiological count and e-Nose signal for three different fish fillet was developed. Once the linear relationship is included into the hand-held unit software, the e-Nose signal can be used for assessment of seafood freshness without performing the microbiological count technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.360-361
• /
• 2006

This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.