• 한국식품과학회지
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• 제29권4호
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• pp.635-640
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• 1997

Potato chip을 제조시 canola유를 선택하여 potato chip을 제조하는 과정에서 발생하는 potato chip의 기름 함량이 40%정도까지 흡수하게 되는데 이 흡수된 기름이 저장과 유통되는 동안 potato chip의 품질을 유지하는데 결정적인 영향을 주므로 항산화제인 BHA, BHT, TBHQ와 silicone유를 첨가한 첨가 유의 항산화제 효과를 관능 검사와 함께 비교 고찰하였다. Potato chips에서 추출한 oil의 항산화제 효과는 canola oil+TBHQ (0.02%)+silicone (10 ppm)에서 가장 우수한 항산화 효과가 있었고 다음은 canola oil+TBHQ로 안정한 것으로 나타났으며 항산화제를 단독으로 사용한 것보다 silicone을 첨가한 것이 탁월한 안정성을 보였고 항산화제로서 TBHQ가 매우 효과가 있었고 silicone를 첨가한 유지에서 탁월한 저장 안정성을 유지하는 것으로 나타났다. 관능검사 결과 canola oil은 2개월부터 overall, flavor, aftertaste의 변화에 약간의 유의차를 나타내었으며 TBHQ과 silicone을 첨가한 oil는 2개월에서는 전 항목에서 변화가 없었고 4개월부터 overall, flavor, freshness, aftertaste의 항목에서 유의차를 나타내었으며 따라서 2개월 정도 저장 안정성이 연장되는 효과가 있는 것으로 나타났다.

• 한국식품과학회지
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• 제14권4호
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• pp.364-369
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• 1982

감마선 조사(照射)와 자연저온(自然低溫)에 의한 감자의 상업적(商業的) 저장법(貯藏法) 개발(開發)을 목표(目標)로 제일보(第一報)와 같은 방법으로 Irish cobbler와 Shimabara 품종(品種)을 7개월(個月) 및 9개월간(個月間) 각각(各各) 저장(貯藏)하면서 potato chip 제조적성(製造適性)에 대한 실험(實驗)을 한 결과(結果)는 다음과 같다. 1. 9개월간(個月間) 저장(貯藏)한 Irish cobbler로 제조(製造)된 potato chip은 기계적(機械的) 및 관능검사결과(官能檢査結果) 대조구(對照區)가 무처리구(無處理區)보다 우수하였다. 2. Potato chip 수율(收率)에 영향이 큰 제피율(除皮率)에 따른 손실은 무처리구(無處理區)가 조사구(照射區)보다 $20{\sim}25%$ 높았다. 3. 단경기(端境期)에 있어서 potato chip 가공원료(加工原料)로써 방사선(放射線)과 자연저온(自然低溫)에 의하여 저장(貯藏)된 감자가 적당하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.263-265
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• 2002

We have used the secondary-step immobilization methods based on the chip pattern of hydrophobic self-assembly layers to assemble microfabricated particles onto the chip pattern. Immobilization of DNA, fabrication of the particles and the chip pattern, arrangement of the particles on the chip pattern, and recognition of each using DNA fluorescence measurement were carried out. Establishing the walls, the arrangement stability of the particles was improved. Each DNA is able to distinguish by using the lithography process on the particles. Advantages of this method are process simplicity, wide applicability and stability. It is thought that this method can be applicable as a new fabrication technology to develop a minute integration type biosensor microarray.

• 한국기계가공학회지
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• 제18권1호
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• pp.101-108
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• 2019

In this study, the hole-cavity resonance technology and the micro pore stainless chip sintering technology were fused to develop silencers with excellent noise attenuation performance even at fluid pressures exceeding 30 bar for the first time at home and abroad. As a result of this study, the noise attenuation performance was greatly improved as reflection, loss, and resonance were made to occur thousands of times simultaneously when fluids pass through the sintered micro pore stainless steel chip sound absorber. The noise of the gas emitted from the bomb without the silencer was shown to be 125dB. And noise test conducted after installation of the silencer showed the noise of 67dB. Given the study results, the amount of noise was greatly reduced in the sintered silencer.

• ETRI Journal
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• 제35권2호
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.845-848
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• 2004

High throughput analysis using a DNA chip microarray is powerful tool in the post genome era. Less labor-intensive and lower cost-performance is required. Thus, this paper aims to develop the multi-channel type label-free DNA chip and detect SNP (Single nucleotide polymorphisms). At first, we fabricated a high integrated type DNA chip array by lithography technology. Various probe DNAs were immobilized on the microelectrode array. We succeeded to discriminate of DNA hybridization between target DNA and mismatched DNA on microarray after immobilization of a various probe DNA and hybridization of label-free target DNA on the electrodes simultaneously. This method is based on redox of an electrochemical ligand.

• 대한의용생체공학회:의공학회지
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• 제38권6호
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• pp.302-307
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• 2017

This paper presents a paper-based concentration gradient chip to analyze colorimetric glucose assay. The paper-based concentration gradient chip was fabricated through a wax patterning technique that can design the fluidic channel by selectively printing hydrophobic and hydrophilic areas. Afterwards, glucose and dilution solutions were loaded into the inlet of a concentration gradient chip and each solution was then mixed sequentially at mixing channel. Finally, concentration gradient was formed at each outlet of the chip. To measure the glucose concentration of the solution in outlets, we conducted colorimetric glucose assay with fixed concentration of glucose solution (0, 5, 10, 15 and 20 mM) and obtained normalized intensity. Subsequently, glucose concentrations of the outlets were calculated by substituting the normalized intensity to linear regression function based on the normalized intensity of fixed glucose concentration. Finally, the concentration gradient of glucose was formed on the chip with the result of colorimetric assay. The concentration gradient paper chip has the potential to accurately analyze unknown glucose concentration.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.