• Title/Summary/Keyword: Chip on chip technology

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Position of Hungarian Merino among other Merinos, within-breed genetic similarity network and markers associated with daily weight gain

  • Attila, Zsolnai;Istvan, Egerszegi;Laszlo, Rozsa;David, Mezoszentgyorgyi;Istvan, Anton
    • Animal Bioscience
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    • v.36 no.1
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    • pp.10-18
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    • 2023
  • Objective: In this study, we aimed to position the Hungarian Merino among other Merinoderived sheep breeds, explore the characteristics of our sampled animals' genetic similarity network within the breed, and highlight single nucleotide polymorphisms (SNPs) associated with daily weight-gain. Methods: Hungarian Merino (n = 138) was genotyped on Ovine SNP50 Bead Chip (Illumina, San Diego, CA, USA) and positioned among 30 Merino and Merino-derived breeds (n = 555). Population characteristics were obtained via PLINK, SVS, Admixture, and Treemix software, within-breed network was analysed with python networkx 2.3 library. Daily weight gain of Hungarian Merino was standardised to 60 days and was collected from the database of the Association of Hungarian Sheep and Goat Breeders. For the identification of loci associated with daily weight gain, a multi-locus mixed-model was used. Results: Supporting the breed's written history, the closest breeds to Hungarian Merino were Estremadura and Rambouillet (pairwise FST values are 0.035 and 0.036, respectively). Among Hungarian Merino, a highly centralised connectedness has been revealed by network analysis of pairwise values of identity-by-state, where the animal in the central node had a betweenness centrality value equal to 0.936. Probing of daily weight gain against the SNP data of Hungarian Merinos revealed five associated loci. Two of them, OAR8_17854216.1 and s42441.1 on chromosome 8 and 9 (-log10P>22, false discovery rate<5.5e-20) and one locus on chromosome 20, s28948.1 (-log10P = 13.46, false discovery rate = 4.1e-11), were close to the markers reported in other breeds concerning daily weight gain, six-month weight, and post-weaning gain. Conclusion: The position of Hungarian Merino among other Merino breeds has been determined. We have described the similarity network of the individuals to be applied in breeding practices and highlighted several markers useful for elevating the daily weight gain of Hungarian Merino.

Genome-wide association study for loin muscle area of commercial crossbred pigs

  • Menghao Luan;Donglin Ruan;Yibin Qiu;Yong Ye;Shenping Zhou;Jifei Yang;Ying Sun;Fucai Ma;Zhenfang Wu;Jie Yang;Ming Yang;Enqin Zheng;Gengyuan Cai;Sixiu Huang
    • Animal Bioscience
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    • v.36 no.6
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    • pp.861-868
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    • 2023
  • Objective: Loin muscle area (LMA) is an important target trait of pig breeding. This study aimed to identify single nucleotide polymorphisms (SNPs) and genes associated with LMA in the Duroc×(Landrace×Yorkshire) crossbred pigs (DLY). Methods: A genome-wide association study was performed using the Illumina 50K chip to map the genetic marker and genes associated with LMA in 511 DLY pigs (255 boars and 256 sows). Results: After quality control, we detected 35,426 SNPs, including six SNPs significantly associated with LMA in pigs, with MARC0094338 and ASGA0072817 being the two key SNPs responsible for 1.77% and 2.48% of the phenotypic variance of LMA, respectively. Based on previous research, we determined two candidate genes (growth hormone receptor [GHR] and 3-oxoacid Co A-transferase 1 [OXCT1]) that are associated with fat deposition and muscle growth and found further additional genes (MYOCD, ARHGAP44, ELAC2, MAP2K4, FBXO4, FBLL1, RARS1, SLIT3, and RANK3) that are presumed to have an effect on LMA. Conclusion: This study contributes to the identification of the mutation that underlies quantitative trait loci associated with LMA and to future pig breeding programs based on marker-assisted selection. Further studies are needed to elucidate the role of the identified candidate genes in the physiological processes involved in LMA regulation.

Adaptive Block Watermarking Based on JPEG2000 DWT (JPEG2000 DWT에 기반한 적응형 블록 워터마킹 구현)

  • Lim, Se-Yoon;Choi, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.101-108
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    • 2007
  • In this paper, we propose and verify an adaptive block watermarking algorithm based on JPEG2000 DWT, which determines watermarking for the original image by two scaling factors in order to overcome image degradation and blocking problem at the edge. Adaptive block watermarking algorithm uses 2 scaling factors, one is calculated by the ratio of present block average to the next block average, and the other is calculated by the ratio of total LL subband average to each block average. Signals of adaptive block watermark are obtained from an original image by itself and the strength of watermark is automatically controlled by image characters. Instead of conventional methods using identical intensity of a watermark, the proposed method uses adaptive watermark with different intensity controlled by each block. Thus, an adaptive block watermark improves the visuality of images by 4$\sim$14dB and it is robust against attacks such as filtering, JPEG2000 compression, resizing and cropping. Also we implemented the algorithm in ASIC using Hynix 0.25${\mu}m$ CMOS technology to integrate it in JPEG2000 codec chip.

Measurements of Lattice Strain in MOCVD-GaN Thin Film Grown on a Sapphire Substrate Treated by Reactive Ion Beam (활성화 이온빔 처리된 Sapphire기판 위에 성장시킨 MOCVD-GaN 박막의 격자변형량 측정)

  • Kim, Hyun-Jung;Kim, Gyeung-Ho
    • Applied Microscopy
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    • v.30 no.4
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    • pp.337-345
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    • 2000
  • Introduction of the buffer layer and the nitridation of a sapphire substrate were one of the most general methods employed for the reduction of lattice defects in GaN thin films Brown on sapphire by MOCVD. In an effort to improve the initial nucleation and growth condition of the GaN, reactive ion beam (RIB) of nitrogen treatment of the sapphire surface has been attempted. The 10 nm thick, amorphous $AlO_xN_y$ layer was formed by RIB and was partially crystallized alter the main growth of GaN at high temperature, leaving isolated amorphous regions at the interface. The beneficial effect of amorphous layer at interface in relieving the thermal stress between substrate and GaN film was examined by measuring the lattice strain value of the GaN film grown with and without the RIB treatment. Higher order Laue zone pattern (HOLZ) of $[\bar{2}201]$ zone axis was compared with simulated patterns and lattice strain was estimated It was confirmed that the great reduction of thermal strain was achieved by RIB process and the amount of thermal stress was 6 times higher in the GaN film grown by conventional method without the RIB treatment.

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Effect of Co Interlayer on the Interfacial Reliability of SiNx/Co/Cu Thin Film Structure for Advanced Cu Interconnects (미세 Cu 배선 적용을 위한 SiNx/Co/Cu 박막구조에서 Co층이 계면 신뢰성에 미치는 영향 분석)

  • Lee, Hyeonchul;Jeong, Minsu;Kim, Gahui;Son, Kirak;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.3
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    • pp.41-47
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    • 2020
  • The effect of Co interlayer on the interfacial reliability of SiNx/Co/Cu thin film structure for advanced Cu interconnects was systematically evaluated by using a double cantilever beam test. The interfacial adhesion energy of the SiNx/Cu thin film structure was 0.90 J/㎡. This value of the SiNx/Co/Cu thin film structure increased to 9.59 J/㎡.Measured interfacial adhesion energy of SiNx/Co/Cu structure was around 10 times higher than SiNx/Cu structure due to CoSi2 reaction layer formation at SiNx/Co interface, which was confirmed by X-ray photoelectron spectroscopy analysis. The interfacial adhesion energy of SiNx/Co/Cu structure decreased sharply after post-annealing at 200℃ for 24 h due to Co oxidation at SiNx/Co interface. Therefore, it is required to control the CoO and Co3O4 formation during the environmental storage of the SiNx/Co/Cu thin film to achieve interfacial reliability for advanced Cu interconnections.

Effect of Post-annealing on the Interfacial adhesion Energy of Cu thin Film and ALD Ru Diffusion Barrier Layer (후속 열처리에 따른 Cu 박막과 ALD Ru 확산방지층의 계면접착에너지 평가)

  • Jeong, Minsu;Lee, Hyeonchul;Bae, Byung-Hyun;Son, Kirak;Kim, Gahui;Lee, Seung-Joon;Kim, Soo-Hyun;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.3
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    • pp.7-12
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    • 2018
  • The effects of Ru deposition temperature and post-annealing conditions on the interfacial adhesion energies of atomic layer deposited (ALD) Ru diffusion barrier layer and Cu thin films for the advanced Cu interconnects applications were systematically investigated. The initial interfacial adhesion energies were 8.55, 9.37, $8.96J/m^2$ for the sample deposited at 225, 270, and $310^{\circ}C$, respectively, which are closely related to the similar microstructures and resistivities of Ru films for ALD Ru deposition temperature variations. And the interfacial adhesion energies showed the relatively stable high values over $7.59J/m^2$ until 250h during post-annealing at $200^{\circ}C$, while dramatically decreased to $1.40J/m^2$ after 500 h. The X-ray photoelectron spectroscopy Cu 2p peak separation analysis showed that there exists good correlation between the interfacial adhesion energy and the interfacial CuO formation. Therefore, ALD Ru seems to be a promising diffusion barrier candidate with reliable interfacial reliability for advanced Cu interconnects.

A 10b 100MS/s 0.13um CMOS D/A Converter Based on A Segmented Local Matching Technique (세그먼트 부분 정합 기법 기반의 10비트 100MS/s 0.13um CMOS D/A 변환기 설계)

  • Hwang, Tae-Ho;Kim, Cha-Dong;Choi, Hee-Cheol;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.62-68
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    • 2010
  • This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

Design of an Energy Management System for On-Chip Solar Energy Harvesting (온칩 태양 에너지 하베스팅을 위한 에너지 관리 시스템 설계)

  • Jeon, Ji-Ho;Lee, Duck-Hwan;Park, Joon-Ho;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.2
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    • pp.15-21
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    • 2011
  • In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

CPW Phase Shifter and Shunt Stub with Air-Bridge Fabricated on Oxidized Porous Silicon(OPS) Substrate (산화된 다공질 실리콘 기판 위에 제작된 에어브리지를 가진 CPW Phase Shifter와 Shunt Stub)

  • Sim, Jun-Hwan;Park, Dong-Kook;Kang, In-Ho;Kwon, Jae-Woo;Park, Jeong-Yong;Lee, Jong-Hyun;Jeon, Joong-Sung;Ye, Byeong-Duck
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.9
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    • pp.11-18
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    • 2002
  • This paper presents a CPW phase shifter and shunt stub with air-bridge on a 10-${\mu}m$-thick oxidized porous silicon(OPS) substrate using surface micromachining. The line dimensions of the CPW phase shifter was designed with S-W-Sg = 100-30-400 ${\mu}m$. And the width and length of the air-bridge with "ㄷ“ shape were 100 ${\mu}m$ and 400-460-400 ${\mu}m$, respectively. In order to achieve low attenuation, stepped air-bridge CPW phase shift was proposed. The insertion loss of the stepped air-bridge CPW phase shift is more improved than that of no stepped air-bridge CPW phase shift. The measured phase characteristic of the fabricated CPW phase shifter is close to 180$^{\circ}$ over a very broad frequency range of 28 GHz. The measured working frequency of short-end series stub is 28.7 GHz and the return loss is - 20 dB. And the measured working frequency of short-end shunt stub is 28.9 GHz and the return loss is - 23 dB at midband. As a result, the pattering of stub in the center conductor of CPW lines can offer size reduction and lead to high density chip layouts.

A Study on Cryptography Scheme and Secure Protocol for Safety Secure Scheme Construction in 13.56Mhz RFID (13.56Mhz RFID 환경에서 안전한 보안 스킴 구축을 위한 암호 스킴 및 보안 프로토콜 연구)

  • Kang, Jung-Ho;Kim, Hyung-Joo;Lee, Jae-Sik;Park, Jae-Pyo;Jun, Moon-Seog
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.3
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    • pp.1393-1401
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    • 2013
  • What is RFID Microchip tag attached to an object, the reader recognizes technology collectively, through communication with the server to authenticate the object. A variety of RFID tags, 13.56Mhz bandwidth RFID card, ISO/IEC 14443 standards based on NXP's Mifare tag occupies 72.5% of the world market. Of the Mifare tags, low cost tag Mifare Classic tag provided in accordance with the limited hardware-based security operations, protocol leaked by a variety of attacks and key recovery vulnerability exists. Therefore, in this paper, Cryptography Scheme and Secure Protocol for Safety Secure Scheme Construction in 13.56Mhz RFID have been designed. The proposed security scheme that KS generated by various fixed values and non-fixed value, S-Box operated, values crossed between LFSR and S-Box is fully satisfied spoofing, replay attacks, such as vulnerability of existing security and general RFID secure requirement. Also, It is designed by considering the limited hardware computational capabilities and existing security schemes, so it could be suit to Mifare Classic now.