• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.155-162
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• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• 한국생산제조학회지
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• 제20권5호
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• 한국생산제조학회지
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• 제23권6호
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• pp.609-617
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• 2014

We have studied a chip-on-board LED lighting optical system for various luminous-intensity-distribution angles of the LED. An optical system that can accept different LEDs was made to reduce the systems's weight and size as we selected the chip-on-board LED, which is easy to apply to optical systems, unlike existing package-on-board LEDs. The luminous-intensity-distribution angles were $45^{\circ}$, $60^{\circ}$, $90^{\circ}$, and $120^{\circ}$. We researched these four types of optical systems. The $45^{\circ}$ and $60^{\circ}$ units were developed into reflectors, and the $90^{\circ}$ and $120^{\circ}$ units, into lenses. We checked the performance of the designed optical system through simulation and made a mock-up. Then we made a prototype of the chip-on-board LED high bay for use with the mock-up. After measuring its performance, we tested the luminous-intensity-distribution angles and compared them with simulation data. The resulting prototype was developed considering brightness, light uniformity, age, and economics which are suitable for a factory environment.

• 조명전기설비학회논문지
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• 제29권4호
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• pp.1-10
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• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1994년도 FIFTH WESTERN PACIFIC REGIONAL ACOUSTICS CONFERENCE SEOUL KOREA
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• ETRI Journal
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• 제33권3호
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• pp.335-343
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• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• Journal of the Korean Wood Science and Technology
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• 제16권2호
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• pp.1-41
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• 1988

톱밥을 보드에 활용(活用)하기 위한 방안(方案)으로서, 톱밥자체의 약(弱)한 결집력(結集力)과 치수불량성(不良性)을 개선(改善)하기 위하여 비(非) 목질계(木質系) 재료(材料)인 폴리프로필렌 사(絲)칩과 배향사(配向絲)를 혼합(混合) 결체(結締)함에 다른 보드의 기초성질(基礎性質)로서 물리적(物理的) 기계적(機械的) 성질(性質)을 고찰(考察)하였는 바, 현재(現在) 제재용(製材用)으로 많이 이용(利用)되고 있는 나왕재(羅王材)(white meranti)의 톱밥에 개질재료(改質材料)로서 비(非) 목질(木質) 계(系) 플라스틱 물질(物質)인 폴리프로필렌 사(絲)를 칩상(狀) 또는 배향사(配向絲)의 형태(形態)로 조제(調製)하여 일반(一般) 성형법(成型法)을 적용(適用)함으로써 톱밥과 결체(結締) 구성(構成)한 톱밥보드를 제조(製造)하였다. 12 및 15%로 하여 구성(構成)하였다. 배향사(配向絲)는 보드폭방향(幅方向)으로 0.5, 1.0 및 1.5cm의 일정(一定)한 간격(間隔)으로 배열(配列)하였다. 위의 조건(條件)에 의(依)해 단(單) 2 3층(層)으로 각기(各己) 구분(區分)제조된 사(絲)칩 또는 배향사(配向絲) 구성(構成) 톱밥보드의 물리적(物理的) 및 기계적(機械的) 성질(性質)을 구명(究明)하였는 바, 그 주요(主要)한 결론(結論)을 요약(要約)하면 다음과 같다. 1. 사(絲)칩 혼합(混合) 단층구성(單層構成)보드의 두께 팽창율(膨脹率)은 톱잡대조(對照)보드의 팽창율보다 모두 낮았다. 사(絲)칩 함량(含量)을 증가(增加) 시킴에 따라서 두께 팽창율은 점차(漸次) 감소(減少)하는 경향이 뚜렷하였다. 한편, 2층구성(層構成)보드는 단층(單層) 구성(構成)보드보다 높은 팽창율을 나타냈으나 대부분이 톱밥대조(對照)보드 보다 팽창율이 낮았다. 3층(層)으로 사(絲)칩구성(構成)한 보드는 톱밥대조(對照)보드보다도 모두 낮은 두께 팽창율을 나타냈다. 2. 사(絲)칩 배향사(配向絲) 구성(構成)보드의 두께 팽창율은 0.5cm 배향간격에서 사(絲)칩함량(含量) 12%와 15%의 길이 1.0cm와 1.5cm로 구성함으로써 단층(單層) 및 3층구성(層構成)보드의 최저치(最低値)보다 더 낮았다. 3. 단층구성(單層構成)보드의 휨강도는 비중(比重) 0.51 구성(構成)보드의 경우 사(絲)칩함량(含量) 3%에서 톱밥대조)對照)보드보다 높은 강도를 나타냈으나, KS F 3104 의 파티클보드 100타입 기준(基準) 값인 80 kgf/$cm^2$에 훨씬 못 미쳤다. 그러나 비중(比重) 0.63 구성(構成)보드에서 함량(含量) 6%의 길이 1.5cm 사(絲)칩 구성과 함량(含量)3% 의 모든 사(絲)칩 길이로 구성한 보드, 그리고 비중(比重) 0.72의 모든 사(絲)칩 구성보드는 KS F 기준값을 훨씬 상회(上廻) 하였다. 2층구성(層構成)보드의 휨강도는 톱밥대조(對照)보드보다도 사(絲)칩구성의 경우 모두 낮았으며 단층구성(單層構成)보드의 휨강도보다도 낮은 값을 나타냈다. 3층구성(層構成)보드의 휨강도는 사(絲)칩 함량(含量) 9% 이하(以下)의 길이 1.5cm 구성보드는 모두 톱밥대조(對照)보드보다 높은 값을 나타냈으며 KSF 기준값을 훨씬 상회(上廻) 하였다. 4. 배향사구성(配向絲構成) 톱밥보드의 경우(境遇), 배향간격(配向間隔)이 좁은 0.5cm에서 가장 높은 휨강도를 나타냈으며, 배향간격이 보다 넓은 1.0cm 와 1.5cm 구성(構成)에서는 휨 강도가 0.5cm 간격 보다 낮았다. 그러나 배향사구성(配向絲構成) 톱밥보드는 모두 톱밥대조(對照)보드 보다 높은 휨강도를 나타냈다. 5. 사(絲칩) 배향사(配向絲) 구성 보드의 휨강도는 거의 대부분(大部分)의 구성보드에서 톱밥대조(對照)보드보다 높은 값을 나타냈으며 KSF 기준값을 훨씬 상회(上廻) 하였다. 특(特)히 배향간격이 좁고, 길이가 긴 사(絲)칩으로 구성한 보드의 휨강도가 높은 값을 나타냈다. 그리고 사(絲)칩을 배향사(配向絲)와 혼합(混合) 구성(構成)할 때 배향사의 간격이 넓어짐에 따라 톱밥과 배향사(配向絲)만으로 구성한 보드보다도 휨 강도가 높아지는 현상(現象)이 나타났다. 6. 단층(單層), 2층(層) 및 3층(層) 구성(構成) 보드의 탄성계수는 대부분(大部分) 톱밥대조(對照)보드 보다 낮은 값을 나타냈다. 그러나 배향사(配向絲) 구성(構成) 톱밥보드에 있어서는, 배향 간격이 0.5, 1.0, 1.5crn로 됨에 따라서 톱밥대조(對照)보드보다도 각각(各各) 20%, 18%, 10% 탄성계수가 증가(增加)되었다. 7. 사(絲)칩 배향사(配向絲) 구성(構成) 보드의 탄성계수(彈性係數)는 배향간격 0.5crn, 1.0cm 및 1.5crn에서 거의 모두 톱밥대조(對照)보드보드보다도 훨씬 높은 값을 나타냈다. 그리고 함량(含量)9% 이하(以下)에서 사(絲)칩길이를 0.5cm이상(以上)으로 구성하였을 때 배향사(配向絲)만을 구성한 톱밥보드보다도 탄성계수가 높아지는 현상(現象)이 나타났는데, 배향(配向)간격이 좁은 경우 사(絲)칩결체(結締)에 의(依)한 탄성계수(彈性係數) 증가효과(增加效果)가 컸다. 8. 사(絲)칩 혼합(混合) 단층구성(單層構成) 보드의 박리저항(剝離抵抗)은 톱밥대조(對照)보드 보다 모두 낮았다. 그러나 비중(比重) 0.63의 사(絲)칩 구성보드는 KS F 3104의 100타입 기준 값인 1.5kgf/$cm^2$를 모두 상회(上廻) 하였고, 비중(比重) 0.72의 사(絲)칩 구성보드는 200타입의 기준값 3kgf/$cm^2$를 상회(上廻)하는 박리저항(剝離抵抗)을 나타냈다. 2층(層), 3층(層) 및 배향구성(配向構成)도 거의 모두 200타입의 기준값 3kgf/$cm^2$를 상회(上廻) 하였다. 9. 단층구성(單層構成)보드의 나사못유지력(維持力)은 사(絲)칩을 혼합 구성한 경우, 대체(大體)로 톱밥대조(對照)보드보다도 낮은 값을 나타냈다. 그러나, 2층(層) 및 3층구성(層構成)보드에서는 사(絲)칩 구성(構成)에 따른 감소경향(減少傾向)이 나타나지 않고 대체로 고른 나사못 유지력을 나타냈다. 또한, 사(絲)칩 배향사(配向絲) 구성(構成)보드에서는 사(絲)칩함량(含量) 9% 이하(以下)에서 거의 모두 톱밥대조(對照)보드 보다도 높은 나사못 유지력을 나타냈다.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.29-33
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• 2002

In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

• 한국생산제조학회지
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• 제21권2호
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• pp.225-231
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• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.