• 한국정밀공학회지
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• 제21권10호
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• pp.188-195
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• 2004

In this paper, we fabricated fluidic devices like micro-channel, pump, mixer and particular gas separator with the technology of stereolithouaphy using RP(rapid-prototyping). The fabricated fluidic devices are expected to be applied to develop Lab-on-a chip type liquid analyzer. Stereolithography technology seems effective for fabricating MEMS(Micro Electro Mechanical System) with complicated structure because it makes three dimensional fabrication possible but, exclusive devices are needed to be developed fur fabricating even more microscopic MEMS structure.

• 한국산학기술학회논문지
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• 제16권9호
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• pp.5748-5755
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• 2015

스크라이빙 공정은 LED 칩 생성을 위한 절단 공정으로 칩의 특성 및 생산량을 결정하는 중요한 공정이다. 기존의 기계적 방식 및 레이저 방식의 스크라이빙 공정은 칩의 열 변형 및 강도 저하, 절단 영역의 제한 등의 문제점이 있다. 이러한 문제를 해결하기 위해 웨이퍼 내부에 공극을 생성하여 자가 균열을 유도하는 내부 레이저 스크라이빙 공정이 연구되고 있으나 LED 칩 제작을 위한 사파이어 웨이퍼의 절단에 대한 연구는 미비한 실정이다. 본 논문은 LED 칩 제작에 사용되는 사파이어 웨이퍼의 내부 레이저 스크라이빙 공정을 적용하기 위해 주요 가공 변수를 정립하고 가공 실험을 통하여 절단 특성을 분석함으로써 내부 레이저 스크라이빙 시스템 구축을 위한 기초 가공 조건을 확립하였다.

• 전자공학회논문지A
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• 제32A권3호
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• pp.89-99
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• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• 한국전자파학회논문지
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• 제13권6호
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• pp.514-520
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• 2002

본 논문에서는 L-band용 이동통신 단말기에 적용 가능한 수신단 MMIC 믹서의 설계 및 제작에 관한 연구를 다룬다. 단일 칩으로 집적하기 적절한 LO 및 RF balun을 능동소자를 이용하여 구성하였으며 각 능동소자의 공정상의 변화를 보상하기 위하여 새롭게 제안된 바이어스 회로를 적용하였다. 믹서의 변환이득은 -14 dB이며 IP3는 약 4 dBm, 포트간 격리도는 25 dB 이상의 값을 가진다. 제안된 새로운 바이어스 회로는 FET와 저항으로 구성되며 공정상의 변화와 온도의 변화 등에 의한 문턱전압의 변화를 보상해 줄 수 있다. 설계된 칩의 사이즈는 1.4 mm$\times$1.4 mm이다.

• 전기학회논문지
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• 제56권11호
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• pp.1967-1971
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• 2007

In this paper, we verified basic forms and equivalent circuits of spiral inductors and various kinds of parasitics of equivalent circuits by using HFSS and Nexxim program that were 3-D EM analysis tools, and fabrication on-chip spiral inductors using Hynix's 0.25um 1-poly and 5-metal CMOS process. Comparing with PGS(patterned ground shield) and NPGS(non patterned ground shield) of spiral inductors of 3.5 turn, 4.5 turn and 5.5 turn, etc, the application of PGS could improve maximum Q value by 8-12%.

• 한국정밀공학회지
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• 제13권11호
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• pp.46-56
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• 1996

Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.286-289
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• 2003

We investigated the influence of the properties of substrate material on the separation efficiency in microchip electrophoresis. We fabricated the various microchips and studied separation efficiency in microchannels composed of a single material such as quartz, glass, polydimethylsiloxane (PDMS), and polymethylmetha crylate (PMMA), as well as hybrid micro channels composed of different materials. New fabrication process for glass chip was suggested and some treatment is added to improve fabrication process in other chip. Separation efficiency was compared by measuring migration times and bandwidths of EOF and analytes in each microchip. The efficiency is the function of migration time, which is affected by the electroosmotic flow (EOF), and bandwidth of an analyte. EOF is highly dependent upon the characteristics of a microchannel wall surface. Migration time was more reproducible in silica chips than that of PDMS chip and more band broadening was observed in the microchip composed of hybrid material due to non-uniformity of surface charge density at the walls of the channel.

• KIEE International Transactions on Electrophysics and Applications
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• 제11C권2호
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• pp.23-27
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• 2001

Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarrays were made by immobilizing many kinds if DNAs on transducers (particles). DNA chip microarrays were prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of micro meter-scale sites. The particles occupied different sites from array to array. Each particle cam be distinguished by a tag that is established on the particle. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using hydrophobic interaction.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.115-118
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• 2002

This paper presents the design method and performance characteristics of a chip-type quadrature hybrid using LTCC-MLC technology. The design method for a chip-type quadrature hybrid is based on lumped element equivalent circuit of quarter-wave transformer. The chip-type quadrature hybrid was miniaturized to a greater extent using multilayer structure and lumped element. The proposed design method can also reduce the undesirable parasitic effects of the chip-type quadrature hybrid. The proposed chip-type quadrature hybrid was designed and fabricated using the proposed design method and the equivalent circuit model of a quarter-wave transformer. Fabrication and measurement of designed chip-type quadrature hybrid show much smaller size than a conventional distributed quadrature hybrid and a good agreement with simulated results.

• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.583-591
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• 2000

It this paper the multilayer chip band pass filter for next generation mobile communication phone is fabricated and designed. For the design the multilayer chip filter of non-contented equivalent circuit and contented equivalent circuit with attenuation pole is presented. Finally it is fabricated and designed using the multilayer chip filter of contented equivalent circuit with attenuation pole. The size insertion loss center frequency and band width of multilayer chip filter are 4.5$\times$3.2$\times$2.0[mm], 3.0[d.B] and 1945$\pm$25 MHz respectively. The multilayer chip filter was fabricated by screen printing with Ag electrode after tape casting. Simulation results of multilayer chip filter are compared with experimental results and found to be in excellent agreements.