• Title/Summary/Keyword: Chip control

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Design and Implementation of Communication Module for Distributed Intelligence Control Using LonWorks (LonWorks를 이용한 분산 지능 제어를 위한 통신 모듈의 설계 및 구현)

  • Choi Jae-Huyk;Lee Tae-Oh
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.8
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    • pp.1654-1660
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    • 2004
  • In this paper, we describes the design and implementation of LonWorks communication module for distributed intelligent control using LonWorks technology of Echelon. LonWorks communication module can be divided hardware and firmware. First, hardwares is divided into microcontroller attaching sensors and LonWorks components for working together control network and data network. Hardwares are consisted of neuron chip, microcontroller, transceiver, LONCard. Second, operating firmware is realized with neuron C using NodeBulider 3.0 development tool. Produced and implemented LonWorks communication module is pretested using LTM-10A, Gizmo 4 I/O board, parallel I/O Interface. For field test, microcontroller module part is tested by HyperTerminal, communication procedure in data network is certified by transmitting and receiving short message using LonMaker for Windows tool. Herewith, LON technology is based on network communication technique using LonWorks.

Simple Digital LCD Backlight Inverter using a Single-chip Microcontroller (단일칩 마이크로컨트롤러를 이용한 간단한 디지털 LCD 백라이트 인버터)

  • Jeong, Gang-Youl
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.2
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    • pp.461-468
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    • 2010
  • This paper presents a simple digital LCD backlight inverter using a single-chip microcontroller. The proposed inverter reduces the ignition voltage and eliminates the current spikes and hence improves the ignition behavior of the cold cathode fluorescent lamp(CCFL). Thus it increases the CCFL's life span. This is achieved by implementing a digital dimming control algorithm, that contains the soft-starting algorithm, all on a single-chip microcontroller. The inverter utilizes the full-bridge resonant circuit topology. The design example along with a simple analysis for the inverter is shown, and the experimental results of the designed prototype results in close agreement with the theoretical analysis and explanation. The overall system's power efficiency is approximately 85%. Compared with conventional inverters, the ignition voltage is reduced by around 30% without any lamp current spike occurring during the dimming control operation.

Wafer Edge Profile Control for Improvement of Removal Uniformity in Oxide CMP (산화막CMP의 연마균일도 향상을 위한 웨이퍼의 에지형상제어)

  • Choi, Sung-Ha;Jeong, Ho-Bin;Park, Young-Bong;Lee, Ho-Jun;Kim, Hyoung-Jae;Jeong, Hae-Do
    • Journal of the Korean Society for Precision Engineering
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    • v.29 no.3
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    • pp.289-294
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    • 2012
  • There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

GCP Chip Automatic Extraction of Satellite Imagery Using Interest Point in North Korea (특징점 추출기법을 이용한 접근불능지역의 위성영상 GCP 칩 자동추출)

  • Lee, Kye Dong;Yoon, Jong Seong
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.37 no.4
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    • pp.211-218
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    • 2019
  • The Ministry of Land, Infrastructure and Transport is planning to launch CAS-500 (Compact Advanced Satellite 500) 1 and 2 in 2019 and 2020. Satellite image information collected through CAS-500 can be used in various fields such as global environmental monitoring, topographic map production, analysis for disaster prevention. In order to utilize in various fields like this, it is important to get the location accuracy of the satellite image. In order to establish the precise geometry of the satellite image, it is necessary to establish a precise sensor model using the GCP (Ground Control Point). In order to utilize various fields, step - by - step automation for orthoimage construction is required. To do this, a database of satellite image GCP chip should be structured systematically. Therefore, in this study, we will analyze various techniques for automatic GCP extraction for precise geometry of satellite images.

An Implementation of Remote Monitoring System for Control Relay (제어용 계전기의 원격감시시스템 구현)

  • Chang, Yong-Hoon;Nam, Jae-hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.11
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    • pp.2100-2106
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    • 2016
  • The automation system uses PLC to monitor the manufacturing process status of the production product and processes the sensor information transmitted from the sensor. In this paper, we propose a remote surveillance system to monitor the status of control relay used in automation system. The proposed system consists of a control relay module, a one-chip processor module, a computer monitoring system, and a database system that inputs and manages the details of the control relay. The computer monitoring system is configured to monitor the operating condition and life time of the control relay. The database is configured so that the input date of the control relay can be input and corrected, and the operating state information of the control relay can be automatically printed. In the remote monitoring system, the failure status of the control relay is recognized in real time, and the time required for normal operation can be minimized by quickly replacing faulty parts.

Design and Implementation of On-Chip Network Architecture for Improving Latency Efficiency (지연시간 효율 개선을 위한 On-Chip Network 구조 설계 및 구현)

  • Jo, Seong-Min;Cho, Han-Wook;Ha, Jin-Seok;Song, Yong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.56-65
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    • 2009
  • As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

Study of micro flip-chip process using ABL bumps (ABL 범프를 이용한 마이크로 플립 칩 공정 연구)

  • Ma, Junsung;Kim, Sungdong;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.2
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    • pp.37-41
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    • 2014
  • One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

The Improvement for Performance of White LED chip using Improved Fabrication Process (제조 공정의 개선을 통한 백색 LED 칩의 성능 개선)

  • Ryu, Jang-Ryeol
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.1
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    • pp.329-332
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    • 2012
  • LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

A Deflection Routing using Location Based Priority in Network-on-Chip (위치 기반의 우선순위를 이용한 네트워크 온 칩에서의 디플렉션 라우팅)

  • Nam, Moonsik;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.108-116
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    • 2013
  • The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

Electroplating process for the chip component external electrode

  • Lee, Jun-Ho
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2000.11a
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    • pp.1-2
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    • 2000
  • In chip plating, several parameters must be taken into consideration. Current density, solution concentration, pH, solution temperature, components volume, chip and media ratio, barrel geometrical shape were most likely found to have an effect to the process yields. The 3 types of barrels utilized in chip plating industry are the onventional rotating barrel, vibrational barrel(vibarrel), and the centrifugal type. Conventional rotating barrel is a close type and is commonly used. The components inside the barrel are circulated by the barrel's rotation at a horizontal axis. Process yield has known to have higher thickness deviation. The vibrational barrel is an open type which offers a wide exposure to electrolyte resulting to a stable thickness deviation. It rotates in a vertical axis coupled with multi-vibration action to facilitate mixed up and easy transportation of components. The centrifugal barrel has its plated work centrifugally compacted against the cathode ring for superior electrical contact with simultaneous rotary motion. This experiment has determined the effect of barrel vibration intensity to the plating thickness distribution. The procedures carried out in the experiment involved the overall plating process., cleaning, rinse, Nickel plating, Tin-Lead plating. Plating time was adjusted to meet the required specification. All other parameters were maintained constant. Two trials were performed to confirm the consistency of the result. The thickness data of the experiment conducted showed thatbthe average mean value obtained from higher vibrational intensity is nearer to the standard mean. The distribution curve shown has a narrower specification limits and it has a reduced variation around the target value. Generally, intensity control in vi-barrel facilitates mixed up and easy transportation of components. However, it is desirable to maintain an optimum vibration intensity to prevent solution intrusion into the chips' internal electrode. A cathodic reaction can occur in the interface of the external and internal electrode. 2H20 + e $\rightarrow$M/TEX> 20H + H2.. Hydrogen can penetrate into the body and create pressure which can cause cracks. At high intensity, the chip's motion becomes stronger, its contact between each other is delayed and so plating action is being controlled. However, the strong impact created by its collision can damage the external electrode's structure there by resulting to bad plating condition.

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