• ETRI Journal
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• 제27권1호
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• 한국CDE학회논문집
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• 제5권2호
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• pp.155-167
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• 2000

To be presented is two-dimensional chip-load analysis for cutting-load smoothing which is needed in unmanned machining and high speed machining of sculptured surfaces. Cutter-engagement angle and effective cutting depth are defined as chip-loads which are the geometrical measures corresponding to cutting-load while machining. The extreme values of chip-loads are geometrically derived in the line-line and line-arc-line blocks of the two-dimensional NC-codes. AFA(automatic feedrate adjustment) strategy for cutting-load smoothing is presented based on the chip-load trajectories.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 전자공학회논문지B
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• 제30B권6호
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• pp.86-92
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• 1993

In this paper, we present a VLSI chip design of Multi-layer Bidirectionsl Associative Memory with good error-correction performance. The MBAM neural chip utilizes inner product implementation schems with binary storage and analog calculation.. Multi-layer can be constructed by direct cascading of these chips, and the number of neurons is expandable by parallel connection of these chips. We made proto-type chips and interface board to test the expansion. Currently the Chip has 32 input nodes, 32 output nodes, and can store up to 48 patterns, 32x48x2 SRAMs are included in the chip.

• 한국정밀공학회지
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• 제15권2호
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• pp.99-106
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• 1998

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• Nuclear Engineering and Technology
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• 제55권3호
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• pp.1015-1020
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• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

• 마이크로전자및패키징학회지
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• 제6권3호
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• pp.19-24
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• 1999

이동통신 부품용으로 이용되는 적층 칩 대역통과 필터를 설계, 제작하였으며 설계된 칩 필터의 크기는 4.5 $\times$ 4.4 $\times$ l.8[mm]이고 중심주파수 및 통과대역은 700[MHz]$\pm$15[MHz], 삽입손실은 3.0[dB]이하이다. 적층 칩 필터의 제조는 $BiNbO_4$에 CuO 0.06wt%, $V_2O_5$ 0.lwt%를 첨가한 조성을 이용하였으며 테이프 캐스팅 후 AE 전극을 스크린 프린팅하여 제작하였다. 제작된 칩 필터의 삽입손실과 중심주파수 및 통과대역은 2.58[dB]와 692.5$\pm$15[MHz]로서 중심주파수는 설계 결과보다 7.5[MHz] 낮았으나 그외의 특성은 설계 결과와 유사함을 볼 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.891-894
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• 2001

In this work, an effort is made to investigate the behavior of a chip, from its initial flow to its final breaking stage. The expression for chip flow in grooved tools is verified analytically using FEM. Cutting parameters like velocity and depth of cut have a profound influence on chip flow behavior. Chip curling increases and, for a given tool geometry, effectiveness of the groove increases with increasing depth of cut. The feasibility of tool design using FEM simulations is also demonstrated. Optimization of tool geometry results in better chip control.

• 한국정밀공학회지
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• 제18권11호
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• pp.101-106
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• 2001

In this work, an effort is made to investigate the behavior of a chip, from its initial flow to its final breaking stage. The expression for chip flow in grooved tools is verified analytically using FEM. Cutting parameters like velocity and depth of cut have a profound influence on chip flow behavior. Chip curling increases and, for a given tool geometry, effectiveness of the groove increases with increasing depth of cut. The feasibility of tool design using FEM simulations is also demonstrated. Optimization of tool geometry results in better chip control.