Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2001.11c
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- Pages.376-379
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- 2001
Test sequence control chip design of logic test using FPGA
FPGA를 이용한 logic tester의 test sequence control chip 설계 및 검증
- Kang, Chang-Hun (Department of Electronics Engineering, Kyungpook National University) ;
- Choi, In-Kyu (Department of Electronics Engineering, Kyungpook National University) ;
- Choi, Chang (Department of Electronics Engineering, Kyungpook National University) ;
- Han, Hye-Jin (Department of information and data communication, Ulsan polytechnic college) ;
- Park, Jong-Sik (Department of Electronics Engineering, Kyungpook National University)
- Published : 2001.11.24
Abstract
In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.
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