• Title/Summary/Keyword: Chemical mechanical planarization

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Electro-chemical Mechanical Deposition for Planarization of Cu Interconnect (Cu 배선의 평탄화를 위한 ECMD에 관한 연구)

  • Jeong, Sukhoon;Seo, Heondeok;Park, Boumyoung;Park, Jaehong;Park, Seungmin;Jeong, Moonki;Jeong, Haedo;Kim, Hyoungjae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.9
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    • pp.793-797
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    • 2005
  • This study introduces Electro-chemical Mechanical Deposition(ECMD) lot making Cu interconnect. ECMD is a novel technique that has ability to deposit planar conductive films on non-planar substrate surfaces. Technique involves electrochemical deposition(ECD) and mechanical sweeping of the substrate surface Preferential deposition into the cavities on the substrate surface nay be achieved through two difference mechanisms. The first mechanism is more chemical and essential. It involves enhancing deposition into the cavities where mechanical sweeping does not reach. The second mechanism involves reducing deposition onto surface that is swept. In this study, we demonstrate ECMD process and characteristic. We proceeded this experiment by changing of distribution of current density on divided water area zones and use different pad types.

Predicting and Interpreting Quality of CMP Process for Semiconductor Wafers Using Machine Learning (머신러닝을 이용한 반도체 웨이퍼 평탄화 공정품질 예측 및 해석 모형 개발)

  • Ahn, Jeong-Eon;Jung, Jae-Yoon
    • The Journal of Bigdata
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    • v.4 no.2
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    • pp.61-71
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    • 2019
  • Chemical Mechanical Planarization (CMP) process that planarizes semiconductor wafer's surface by polishing is difficult to manage reliably since it is under various chemicals and physical machinery. In CMP process, Material Removal Rate (MRR) is often used for a quality indicator, and it is important to predict MRR in managing CMP process stably. In this study, we introduce prediction models using machine learning techniques of analyzing time-series sensor data collected in CMP process, and the classification models that are used to interpret process quality conditions. In addition, we find meaningful variables affecting process quality and explain process variables' conditions to keep process quality high by analyzing classification result.

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A Study on 0.13μm Cu/Low-k Process Setup and Yield Improvement (0.13μm Cu/Low-k 공정 Setup과 수율 향상에 관한 연구)

  • Lee, Hyun-Ki;Chang, Eui-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.4
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    • pp.325-331
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    • 2007
  • In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

Enhancement of SiO2 Uniformity by High-Pressure Deuterium Annealing (고압 중수소 어닐링을 통한 SiO2 절연체의 균일성 개선)

  • Yong-Sik Kim;Dae-Han Jung;Hyo-Jun Park;Ju-Won Yeon;Tae-Hyun Kil;Jun-Young Park
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.2
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    • pp.148-153
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    • 2024
  • As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher chip density, thin-film layers have been deposited iteratively. The poor film uniformity resulting from deposition or chemical mechanical planarization (CMP) significantly affects chip yield. Therefore, the development of novel fabrication processes to enhance film uniformity is required. In this context, high-pressure deuterium annealing (HPDA) is proposed to reduce the surface roughness resulting from the CMP. The HPDA is carried out in a diluted deuterium atmosphere to achieve cost-effectiveness while maintaining high pressure. To confirm the effectiveness of HPDA, time-of-flight secondary-ion mass spectrometry (ToF-SIMS) and atomic force microscopy (AFM) are employed. It is confirmed that the absorbed deuterium gas facilitates the diffusion of silicon atoms, thereby reducing surface roughness.

Wafer Edge Profile Control for Improvement of Removal Uniformity in Oxide CMP (산화막CMP의 연마균일도 향상을 위한 웨이퍼의 에지형상제어)

  • Choi, Sung-Ha;Jeong, Ho-Bin;Park, Young-Bong;Lee, Ho-Jun;Kim, Hyoung-Jae;Jeong, Hae-Do
    • Journal of the Korean Society for Precision Engineering
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    • v.29 no.3
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    • pp.289-294
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    • 2012
  • There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

Fluid-Structure Interaction Modeling and Simulation of CMP Process for Semiconductor Manufacturing

  • Sung, In-Ha;Yang, Woo-Yul;Kwark, Ha-Slomi;Yeo, Chang-Dong
    • Transactions of the Society of Information Storage Systems
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    • v.7 no.2
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    • pp.60-64
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    • 2011
  • Chemical mechanical planarization is one of the core processes in fabrication of semiconductors, which are increasingly used for information storage devices like solid state drives. For higher data capacity in storage devices, CMP process is required to show ultimate precision and accuracy. In this work, 2-dimensional finite element models were developed to investigate the effects of the slurry particle impact on microscratch generation and the phenomena generated at pad-particle-wafer contact interface. The results revealed that no plastic deformation and corresponding material removal could be generated by simple impact of slurry particles under real CMP conditions. From the results of finite element simulations, it could be concluded that the pad-particle mixture formed in CMP process would be one of major factors leading to microscratch generation.