• Ocean Systems Engineering
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• v.1 no.4
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• pp.263-283
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• 2011

The performance of a rig tie-down system on a TLP (Tension Leg Platform) is investigated for 10-year, 100-year, and 1000-year hurricane environments. The inertia loading on the derrick is obtained from the three-hour time histories of the platform motions and accelerations, and the dynamic wind forces as well as the time-dependent heel-induced gravitational forces are also applied. Then, the connection loads between the derrick and its substructure as well as the substructure and deck are obtained to assess the safety of the tie-down system. Both linear and nonlinear inertia loads on the derrick are included. The resultant external forces are subsequently used to calculate the loads on the tie-down clamps at every time step with the assumption of rigid derrick. The exact dynamic equations including nonlinear terms are used with all the linear and second-order wave forces considering that some dynamic contributions, such as rotational inertia, centripetal forces, and the nonlinear excitations, have not been accounted for in the conventional engineering practices. From the numerical simulations, it is seen that the contributions of the second-order sum-frequency (or springing) accelerations can be appreciable in certain hurricane conditions. Finally, the maximum reaction loads on the clamps are obtained and used to check the possibility of slip, shear, and tensile failure of the tie-down system for any given environment.

• Nuclear Engineering and Technology
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• v.14 no.1
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• pp.22-40
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• 1982

The nuclear LS-energy matrix elements have been calculated with the harmonic oscillator shell model wave functions for the configurations ( $l_{i}$ $l_{i+1}$｜ $l_{i}$ $l_{i+1}$) where 1$_1$= $l_{s}$ , $l_2$=lp, $l_3$=ld, 2s, $l_4$=1f, 2p, $l_{5}$ =1g, 2d, 3s. The resulting matrix elements are expressed in terms of both Talmi integrals $I_1$ and Slater integrals $F^{k}$ . In addition to this various sum rules are derived and applied to check the results of the calculations.ons.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.648-658
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• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Journal of Communications and Networks
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• v.15 no.2
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• pp.217-221
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• 2013

Quantum low-density parity-check (LDPC) codes based on the Calderbank-Shor-Steane construction have low encoding and decoding complexity. The sum-product algorithm(SPA) can be used to decode quantum LDPC codes; however, the decoding performance may be significantly decreased by the many four-cycles required by this type of quantum codes. All four-cycles can be eliminated using the entanglement-assisted formalism with maximally entangled states (ebits). The proposed entanglement-assisted quantum error-correcting code based on Euclidean geometry outperform differently structured quantum codes. However, the large number of ebits required to construct the entanglement-assisted formalism is a substantial obstacle to practical application. In this paper, we propose a novel class of entanglement-assisted quantum LDPC codes constructed using classical Euclidean geometry LDPC codes. Notably, the new codes require one copy of the ebit. Furthermore, we propose a construction scheme for a corresponding zigzag matrix and show that the algebraic structure of the codes could easily be expanded. A large class of quantum codes with various code lengths and code rates can be constructed. Our methods significantly improve the possibility of practical implementation of quantum error-correcting codes. Simulation results show that the entanglement-assisted quantum LDPC codes described in this study perform very well over a depolarizing channel with iterative decoding based on the SPA and that these codes outperform other quantum codes based on Euclidean geometries.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.189-195
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• 2008

The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.