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http://dx.doi.org/10.6109/jkiice.2010.14.4.939

An analysis of optimal design conditions of LDPC decoder for IEEE 802.11n Wireless LAN Standard  

Jung, Sang-Hyeok (고등기술연구원 로봇생산기술센터)
Na, Young-Heon (금오공과대학교 전자공학과)
Shin, Kyung-Wook (금오공과대학교 전자공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.4, 2010 , pp. 939-947 More about this Journal
Abstract
The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.
Keywords
LDPC; error correction code; LLR approximation; IEEE 802.11n;
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