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http://dx.doi.org/10.5573/ieie.2016.53.12.042

Efficient AT-Complexity Generator Finding First Two Minimum Values for Bit-Serial LDPC Decoding  

Lee, Jea Hack (Department of Electrical and Computer Engineering, Ajou University)
Sunwoo, Myung Hoon (Department of Electrical and Computer Engineering, Ajou University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.12, 2016 , pp. 42-49 More about this Journal
Abstract
This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.
Keywords
Low-density parity-check(LDPC) decoder; min-sum algorithm; area-time complexity; low-complexity design; bit-serial scheme;
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Times Cited By KSCI : 1  (Citation Analysis)
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