1 |
C. Wey, M. Shieh, and S. Lin, "Algorithms of finding the first two minimum values and their hardware implementation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3430-3437, Dec. 2008.
DOI
|
2 |
S. Jung, K. Shin. "A design of LDPC decoder for IEEE 802.11n wireless LAN," The Institute of Electronics Engineers of Korea-Semiconductor and Devices, vol. 62, no. 5, pp. 31-40. Nov. 2010.
|
3 |
Y. Lee, B. Kim, J. Jung, and I.-C. Park, "Low-complexity tree architecture for finding the first two minima," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 1, pp. 61-64, Jan. 2015.
DOI
|
4 |
G. Xiao, M. Martina, G. Masera, and G. Piccinini, "A parallel radix sort-based VLSI architecture for finding the first W maximum/minimum values," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 11, pp. 890-894, Nov. 2014.
DOI
|
5 |
R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA, USA: MIT Press, 1963.
|
6 |
J. Kim and W. Sung, "Rate-0. 96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1004-1015, May 2014.
DOI
|
7 |
S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.
|
8 |
G. Dong, N. Xie, and T. Zhang, "On the use of soft-decision error correction codes in NAND flash memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 2, pp. 429-439, Feb. 2011.
DOI
|
9 |
IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements Part 3: Carrier Sense Multiple Access With Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Std.802.3an, Sep. 2006.
|
10 |
A. Morello and V. Mignone, "DVB-S2: The second generation standard for satellite broad-band services," Proc. IEEE, vol. 94, no. 1, pp. 210-227, Jan. 2006.
DOI
|
11 |
A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Power reduction techniques for LDPC decoders," IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1835-1845, Aug. 2008.
DOI
|
12 |
F. Cai, X. Zhang, D. Declercq, S. Planjery, and B. Vasic, "Finite alphabet iterative decoders for LDPC codes: Optimization, architecture and analysis," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 5, pp. 1366-1375, May 2014.
DOI
|
13 |
F. Gutierrez, G. Corral-Briones, D. Morero, T. Goette, and F. Ramos, "FPGA implementation of the parity check node for min-sum LDPC decoders," in Proc. Conf. Programmable Logic, Mar. 2012, pp. 1-6.
|
14 |
P. A. Marshall, V. C. Gaudet, and D. G. Elliott, "Deeply pipelined digit serial LDPC decoding," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2934-2944, Dec. 2012.
DOI
|
15 |
J. Li, J. Ma, and G. He, "A memory efficient parallel layered QC-LDPC decoder for CMMB systems," Integr., VLSI J., vol. 46, no. 4, pp. 359-368, Sep. 2013.
DOI
|