• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.3
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• pp.226-232
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• 2023

As a potential alternative to flash memory, HfO₂/Al₂O₃ stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO₂/Al₂O₃ stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO₂ layer, the memory window of the 5-layered stack increased by 152.4% after O₂ annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO₂/Al₂O₃ stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O₂ and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

• Journal of Information Display
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• v.9 no.2
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• pp.14-17
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• 2008

A charge trapping host structure was developed to improve the light-emitting efficiency of green phosphorescent organic light-emitting diodes. N, N'-dicarbazolyl-3,5-benzene(mCP) and a spirobifluorene based triplet host(PHl) were co-deposited as hosts in the emitting layer and the device performance was examined according to the composition mCP and PH1. The results showed that the quantum efficiency could be improved by 30 % using a mixed host of mCP and PH1.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.970-973
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• 1999

When the size of the device is decreased, the hot carrier degradation presents a severe problem for long-term device reliability. In this paper we fabricated & tested the 0.26${\mu}{\textrm}{m}$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the characteristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve and charge trapping using the Hp4145 device tester As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially a hot carrier lifetime(nitride oxide gate device satisfied 30years, but the lifetime of wet gate oxide was only 0.1year), variation of Vg, charge to breakdown and charge trapping etc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.310-310
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• 2016

최근 NAND flash memory는 높은 집적성과 데이터의 비휘발성, 낮은 소비전력, 간단한 입, 출력 등의 장점들로 인해 핸드폰, MP3, USB 등의 휴대용 저장 장치 및 노트북 시장에서 많이 이용되어 왔다. 특히, 최근에는 smart watch, wearable device등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 유연하고 투명한 메모리 소자에 대한 연구가 다양하게 진행되고 있다. 대표적인 플래시 메모리 소자의 구조로 charge trapping type flash memory (CTF)가 있다. CTF 메모리 소자는 trap layer의 trap site를 이용하여 메모리 동작을 하는 소자이다. 하지만 작은 window의 크기, trap site의 열화로 인해 메모리 특성이 나빠지는 문제점 등이 있다. 따라서 최근, trap layer에 다양한 물질을 적용하여 CTF 소자의 문제점을 해결하고자 하는 연구들이 진행되고 있다. 특히, 산화물 반도체인 zinc oxide (ZnO)를 trap layer로 하는 CTF 메모리 소자가 최근 몇몇 보고 되었다. 산화물 반도체인 ZnO는 n-type 반도체이며, shallow와 deep trap site를 동시에 가지고 있는 독특한 물질이다. 이 특성으로 인해 메모리 소자의 programming 시에는 deep trap site에 charging이 일어나고, erasing 시에는 shallow trap site에 캐리어들이 쉽게 공급되면서 deep trap site에 갇혀있던 charge가 쉽게 de-trapped 된다는 장점을 가지고 있다. 따라서, 본 실험에서는 산화물 반도체인 ZnO를 trap layer로 하는 CTF 소자의 메모리 특성을 확인하기 위해 간단한 구조인 metal-oxide capacitor (MOSCAP)구조로 제작하여 메모리 특성을 평가하였다. 먼저, RCA cleaning 처리된 n-Si bulk 기판 위에 tunnel layer인 SiO2 5 nm를 rf sputter로 증착한 후 furnace 장비를 이용하여 forming gas annealing을 $450^{\circ}C$에서 실시하였다. 그 후 ZnO를 20 nm, SiO2를 30 nm rf sputter로 증착한 후, 상부전극을 E-beam evaporator 장비를 사용하여 Al 150 nm를 증착하였다. 제작된 소자의 신뢰성 및 내구성 평가를 위해 상온에서 retention과 endurance 측정을 진행하였다. 상온에서의 endurance 측정결과 1000 cycles에서 약 19.08%의 charge loss를 보였으며, Retention 측정결과, 10년 후 약 33.57%의 charge loss를 보여 좋은 메모리 특성을 가지는 것을 확인하였다. 본 실험 결과를 바탕으로, 차세대 메모리 시장에서 trap layer 물질로 산화물 반도체를 사용하는 CTF의 연구 및 계발, 활용가치가 높을 것으로 기대된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.130-134
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• 2015

This research proposes the use of a composition modulated (ZrO₂)_x(Al₂O₃)_1-x film as a charge trapping layer for charge trap flash memory; this is possible when the Zr (Al) atomic percent is controlled to form a variable bandgap as identified by the valence band offsets and electron energy loss spectrum measurements. Compared to memory devices with uniform compositional (ZrO₂)_0.1(Al₂O₃)_0.9 or a (ZrO₂)_0.92(Al₂O₃)_0.08 trapping layer, the memory device using the composition modulated (ZrO₂)_x(Al₂O₃)_1-x as the charge trapping layer exhibits a larger memory window (6.0 V) at the gate sweeping voltage of ±8 V, improved data retention, and significantly faster program/erase speed. Improvements of the memory characteristics are attributed to the special energy band alignments resulting from non-uniform distribution of elemental composition. These results indicate that the composition modulated (ZrO₂)_x(Al₂O₃)_1-x film is a promising candidate for future nonvolatile memory device applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1203-1205
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• 2007

Confinement of charge carrier and exciton is the essential factor for enhancing the efficiency and stability of the electrophosphorescent devices. The interplay between the properties of emitters and other adjacent layers are studied based on the physical interpretation with difference of energy level, charge carrier mobility, and corresponding charge-trapping behavior.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.