• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.185.1-185.1
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• 2009

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.664-674
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• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.73-76
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• 2014

$Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.103-106
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• 2004

We have studied a conduction mechanism and equivalent circuit analysis in $Alq_3$ based Organic Light Emitting Diode. The conduction mechanism in organic light emitting diode can be classified into three regions; ohmic region, space-charge-limited current (SCLC) region and trap-charge-limited current (TCLC) region depending on the region of applied voltage. Equivalent circuit model of organic light emitting diode can be established using a parallel combination of resistance $R_p$ and capacitance $C_p$ with a small series resistance $R_s$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.531-532
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• 2005

We have used ITO/$Alq_3$/Al structure to study electrical conduction mechanism in $Alq_3$ based organic light emitting diode. Current-voltage characteristics were measured at room temperature by varying the thickness of $Alq_3$ layer from 60 to 400nm. We were able to prove that there are three different mechanism depending on the applied voltage; Ohmic, SCLC (space-charge-limited current). and TCLC (trap-charge -limited current) mechanism.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• Journal of IKEEE
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• v.27 no.3
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• pp.303-307
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• 2023

In this paper, the creation of an Electron-Hole Pair due to Total Ionizing Dose (TID) effects inside the oxide of a Buried Channel Array Transistor (BCAT) device is induced, resulting in an increase in leakage current and threshold due to an increase in hole trap charge at the oxide interface. By comparing and simulating changes in voltage with the previously proposed Partial Isolation Buried Channel Array Transistor (Pi-BCAT) structure, the characteristics in leakage current and threshold voltage changed regardless of the increased oxide area of the Pi-BCAT device, compared to the asymmetrically doped BCAT structure. It shows superiority.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1061-1064
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• 2009

Through dark injection space-charge-limited current (DI-SCLC) and trap-free SCLC measurements, it has been demonstrated that an indium tin oxide (ITO)/buckminsterfullerene ($C_{60}$) electrode can form a quasi-Ohmic contact with N, N'-bis (naphthalen-1-yl)-N, N'-bis(phenyl) benzidine (NPB). The DI-SCLC results show a clear peak current along with a shift of the peak position as the field intensity varies, implying an Ohmic (or quasi-Ohmic) contact. A theoretical simulation of the SCLC also shows that ITO/$C_{60}$ forms an Ohmic contact with NPB. The Ohmic contact makes it possible to estimate the NPB hole mobility through the use of both DI-SCLC and trap-free SCLC analysis. This also contributes to a reduction in power consumption.