• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.2
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• pp.97-101
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• 2003

New Pt/Ti and hi/Ti double-metal structures have been investigated for the application of a diffusion barrier between Cu and Si in deep submicron integrated circuits. Pt/Ti and Ni/Ti were deposited using E-beam evaporator at room temperature. The performance of Pt/Ti and Ni/Ti structures as diffusion barrier against Cu diffusion was examined by charge pumping method, gate leakage current, junction leakage current, and SIMS(secondary ion mass spectroscopy). These evaluation indicated that Pt/Ti(200${\AA}$/100${\AA}$) film is a good barrier against Cu diffusion up to 450$^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.2
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• pp.76-81
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• 2004

This paper deals with characteristic analysis and experiments on components of low-Tc(LTS) power supply. A LTS power supply consists of two exciters, a rotor, a stator, and an LTS magnet. The power supply has eight rotating poles, which make rotational magnetic flux. These flux penetrate superconducting sheets and cause currents which charge an LTS load. In this experiment, a 25.8mH LTS magnet was used, and rotor revolutions from 30 to 300rpm were used. In order to measure the pumping-current with respect to the magnet flux changes, a hall sensor was installed at the center of the LTS magnet. The experimental observations have been compared with the theoretical predictions. In this experiment, the pumping-current has reached about 372A.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.283-287
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• 2002

To remedy both the degradation and saturation of the output voltages in the modified Dickson pump. a new multi-stage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94 even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.7
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• pp.438-442
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• 2014

Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Progress in Superconductivity and Cryogenics
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• v.11 no.3
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• pp.40-45
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• 2009

Many superconductor applications such as MRI and SMES must be operated in persistent current mode to eliminate the electrical ohmic loss. This paper presents the characteristic analysis of the high temperature superconducting (HTS) power supply made of YBCO coated conductor (CC). In this research, we have manufactured the HTS power supply to charge the 0.73 mH HTS double-pancake magnet made of YBCO CC. Among the all design parameters, the heater triggerring time and magnet applying time were the most important factors for the best performance of the HTS power supply. In this paper, three-dimensional simulation through finite element method (FEM) was used to study the heat transfer in YBCO CC and the magnetic field of the magnetic circuit. Based upon these results, the final operational sequence could be determined to generate the pumping current. In the experiment, the maximum pumping current reached about 16 A.

• Journal of Power Electronics
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• v.6 no.4
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• pp.298-306
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• 2006

A high efficiency and low cost sustain driver for a plasma display panel (PDP) utilizing a current pumping method is proposed. The main concept of the proposed circuit is using the current source to charge and discharge the panel. As a result, all power switches can achieve zero voltage switching (ZVS) and every auxiliary switch can also achieve zero current switching (ZCS). Since the inductor current can compensate for the discharge current, the current stress of all the power switches can be reduced considerably. Furthermore, it has features such as a simpler structure, less mass, lower cost, and lower electromagnetic interference than in previous circuits.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.