• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• International Journal of Advanced Culture Technology
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• 제9권1호
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• pp.203-209
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• 2021

When carrying out computer programming, the process of checking and correcting errors in the source code is essential work for the completion of the program. Non-computer majors who are learning programming for the first time receive feedback from instructors to correct errors that occur when writing the source code. However, in a learning environment where the time for the learner to practice alone is long, such as an online learning environment, the learner starts to feel many difficulties in solving program errors by himself/herself. Therefore, training on how to check and correct errors after writing the program source code is necessary. In this paper, various types of errors that can occur in a Python program were described, the errors were classified into simple errors and complex errors according to the characteristics of the errors, and the distributions of errors by Python grammar category were analyzed. In addition, a coding learning process to refer error lists was designed to present a coding learning method that enables learners to solve program errors by themselves.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.40-43
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• 2000

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

• 기술혁신학회지
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• 제5권2호
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• pp.212-227
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• 2002

This study reviews the institutional frameworks of Open Source software and develops the stylized facts of Open Source software innovation. Open Source software have to solve two difficult problems for encouraging innovation. First, the source code of Open Source software program should be open and freely distributed and it is very difficult for developers to appropriate the results of their investments. Second, as Open Source software development process is characterized by the participation of communities of developers, it is not easy to coordinate and manipulate the development process. These difficulties of developing Open Source Software have been solved by the particular incentive schemes and coordinating mechanisms. This study reviews the study on the motivation of Open Source software development and the mechanisms which coordinate innovation process of Open Source software with peer review and meritocracy, and how these characteristics promote innovation in Open Source software communities.

• 대한전자공학회논문지
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• 제10권6호
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• pp.62-71
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• 1973

능동 filter에 쓰에는 Gyrator를 구성하여 그 특성을 ECAP(Electronic Circuit Analysis Program)로써 해석하였고 그 결과로 나타난 문제점을 해결하고 특성을 개선하기 위한 조치로서 Colletor 측의 저항을 높이기 위하여 정전류전원회로를 이용하여 전원전압을 줄이고 ECAP로써 해석하여 그 조치가 정당함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.181-191
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• 2018

Rapid development of information technology makes our environment become smarter and massive high performance computers are providing powerful computing for that. Graphics Processing Unit (GPU) as a typical high performance component is being widely used for both graphics and general-purpose applications. Although it can greatly improve computing power, it also delivers significant power consumption and need sufficient power supplies. To make high performance computing more sustainable, the important step is to measure it. Current power technologies for GPU have some drawbacks, such as they are not applicable for power estimation at the early stage. In this article, we present a novel power technology to correlate power consumption and the characteristics at the programmer perspective, and then to estimate power consumption of source program without prerunning. We conduct experiments on Nvidia's GT740 platform; the results show that our power model is more accurately than regression model and has an average error of 2.34% and the maximum error of 9.65%.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 컴퓨터교육학회논문지
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• 제18권4호
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• pp.63-70
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• 2015

프로그램 소스코드는 텍스트를 기반으로 하는 정보이며 동시에 논리 구조를 포함하고 있는 복잡한 구문의 집합체이다. 특히 소스코드의 규모가 수만 라인에 이르는 경우 구조적, 논리적인 복잡함으로 인해 기존의 빅데이터 시각화 기법이 잘 적용되기 힘들다는 문제가 발생한다. 본 논문은 소스코드가 갖는 구조적인 특징을 시각화하는데 있어 필요한 절차를 제안한다. 이를 위해 본 논문은 파싱 과정을 거쳐 생성된 추상구문트리를 대상으로 프로그램의 구조특징을 표현하기 위한 자료형의 정의, 함수간 호출관계를 표현한다. 이들 정보를 바탕으로 제어 정보를 네트워크 형태로 시각화함으로써 모듈의 구조적인 특징을 개괄적으로 살펴볼 수 있는 방법을 제시한다. 본 연구의 결과는 대규모 소프트웨어의 구조적 특징을 이해하거나 변경을 관리하는 효과적인 수단으로 활용할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.