• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.497-497
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• 2013

Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.431-431
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• 2011

Graphene, two dimensional sheet of sp2-hybridized carbon, has attracted an enormous amount of interest due to excellent electrical, chemical and mechanical properties for the application of transparent conducting films, clean energy devices, field-effect transistors, optoelectronic devices and chemical sensors. Especially, graphene is promising candidate to detect the gas molecules and biomolecules due to the large specific surface area and signal-to-noise ratios. Despite of importance to the disease diagnosis, there are a few reports to demonstrate the graphene- and rGO-FET for biological sensors and the sensing mechanism are not fully understood. Here we describe scalable and facile fabrication of rGO-FET with the capability of label-free, ultrasensitive electrical detection of a cancer biomarker, prostate specific antigen/${\alpha}1$-antichymotrypsin (PSA-ACT) complex, in which the ultrathin rGO sensing channel was simply formed by a uniform self-assembly of two-dimensional rGO nanosheets on aminated pattern generated by inkjet printing. Sensing characteristics of rGO-FET immunosensor showed the highly precise, reliable, and linear shift in the Dirac point with the analyte concentration of PSA-ACT complex and extremely low detection limit as low as 1 fg/ml. We further analyzed the charge doping mechanism, which is the change in the charge carrier in the rGO channel varying by the concentration of biomolecules. Amenability of solution-based scalable fabrication and extremely high performance may enable rGO-FET device as a versatile multiplexed diagnostic biosensor for disease biomarkers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.1-7
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• 2011

In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• Nuclear Engineering and Technology
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• v.53 no.7
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• pp.2364-2370
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• 2021

The ⁿMCP (Neutron sensitive microchannel plate) combined with advanced readout electronics is widely used in energy selective neutron imaging because of its good spatial and timing resolution. Neutron detection efficiency is a crucial parameter for the ⁿMCP. In this paper, a mathematical model based on the oblique cylindrical channel and elliptical pore was established to calculate the neutron absorption probability, the escape probability of charged particles and overall detection efficiency of ⁿMCP and analyze the effects of neutron incident position, pore diameter, wall thickness and bias angle. It was shown that when the doping concentration of the ⁿMCP was 10 mol%, the thickness of ⁿMCP was 0.6 mm, the detection efficiency could reach maximum value, about 24% for thermal neutrons if the pore diameter was 6 ㎛, the wall thickness was 2 ㎛ and the bias angle was 3 or 6°. The calculated results are of great significance for evaluating the detection efficiency of the ⁿMCP. In a subsequent companion paper, the mathematical model would be extended to the case of the spatial resolution and detection efficiency optimization of the coating ⁿMCP.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).