• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.396-397
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• 2011

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a $0.13-{\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Annals of Clinical Neurophysiology
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• v.2 no.1
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• pp.8-12
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• 2000

Purpose : The rapid development and wide popularity of Digital EEG(DEEG) is due to its convenience, accuracy and applicability for quantitative analysis. These advantages of DEEG make one hesitate to use analog EEG(AEEG). To assess the advantage of DEEG system utilizing AEEG(DAEEG) over conventional AEEG and the clinical applicability, a DAEEG system was developed and applied to animal model Methods : Sprague-Dawley rat as status epilepticus model were used for collecting the EEG data. After four epidural electrodes were inserted and connected to 8-channel analog EEG(Nihon-Kohden, Japan), continous. EEG monitoring via computer screen was done from two rats simultaneously. EEG signals through analog amplifier and filters were digitized at digital signal processor and stored in Windows-based pentium personal computer. Digital data were sampled at a rate of 200 Hz and 12 bit of resolution. Acquisition software was able to carry out 'real-time view, sensitivity control and event marking' during continuous EEG monitoring. Digital data were stored on hard disk and hacked-up on CD-ROM for off-line review. Review system consisted of off-line review, saving and printing out interesting segment and annotation function. Results: This DAEEG system could utilize most major functions of DEEG sufficiently while making a use of an AEEG. It was easy to monitor continuously compared to Conventional AEEG and to control sensitivity during ictal period. Marking the event such as a clinical seizure or drug injection was less favorable than AEEG due to slowed processing speed of digital processor and central processing unit. Reviewing EEG data was convenient, but paging speed was slow. Storage and management of data was handy and economical. Conclusion : Relatively simple digital EEG system utilizing AEEG can be set-up at n laboratory level. It may be possible to make an application for clinical purposes.

• Journal of Biomedical Engineering Research
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• v.17 no.4
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• pp.449-458
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• 1996

Most of the conventional electrocardiowaphs foil to detect signals other than P-QRS-T due to the limited SNR and bandwidth. High-resolution electrocardiography(HRECG) provides better SNR and wider bandwidth for the detection of micro-potentials with higher frequency components such as vontricular late potentials(LP). We have developed a HRECG using uncorrected XYZ lead for the detection of LPs. The overall gain of the amplifier is 4000 and the bandwidth is 0.5-300Hz without using 60Hz notch filter. Three 16-bit A/D converters sample X, Y, and Z signals simultaneously with a sampling frequency of 2000Hz. Sampled data are transmitted to a PC via a DMA-controlled, optically-coupled serial communication channel. In order to further reduce the noise, we implemented a signal averaging algorithm that averaged many instances of aligned beats. The beat alignment was carried out through the use of a template matching technique that finds a location maximizing cross-correlation with a given beat tem- plate. Beat alignment error was reduced to $\pm$0.25ms. FIR high-pass filter with cut-off frequency of 40Hz was applied to remove the low frequency components of the averaged X, Y, and Z signals. QRS onset and end point were determined from the vector magnitude of the sigrlaIL and some parameters needed to detect the existence of LP were estimated. The entire system was designed for the easy application of the future research topics including the optimal lead system, filter design, new parameter extraction, etc. In the developed HRECG, without signal averaging, the noise level was less than 5$\mu$V$_rms RTI$. With signal averaging of at least 100 beats, the noise level was reduced to 0.5$\mu$V$_rms RTI$, which is low enough to detect LPs. The developed HRECG will provide a new advanced functionality to interpretive ECG analyzers.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2261-2266
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• 2009

A novel adaptive phase calibration method is proposed for nonlinear amplifiers. Based on the adaptive process of simple phase vector calculations, the AM/PM distortion can be significantly reduced for various input power. The performance of the proposed method is evaluated for up to 80 % improvements in AM/PM distortions, compared with the distortion of a conventional amplifier. Moreover, by means of an additional envelope-compensation technique, the improvement of the adjacent channel power ratio (ACPR) is presented.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.59-67
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• 2006

We demonstrate bidirectional long-reach 35-channel dense wavelength division multiplexing-passive optical network(DWDM-PON) based on wavelength-locked Fabry-Perot laser diodes (F-P LDs). The mode control of F-P LD enhances output power at decreased the required injection power. We show packet-loss-free transmission in all 70 channels at 125 Mb/s per channel line rate through 70 km of single mode fiber without optical amplifier The DWDM-PON can consolidate a metro network into an access network by bypassing the central offices within its reach. The proposed DWDM-PON can accommodate about 80 subscribers with an EDFA-based broadband light source. Further expansion up to 100 subscribers is possible with a semiconductor-based BLS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.11
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• pp.1275-1284
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• 2010

100 MHz bandwidth and 1 Gbit/s data speed are needed in LTE-advanced for the next generation mobile communication system. Therefore, spectrum aggregation method has been studied recently to extend usable frequency bands. Also bandwidth utilization is increased since vacant frequencies are used to communicate. However, transceiver structure requires the digital RF and SDR. Therefore, frequency synthesizer and PA must operate over wide-bandwidth and RF impairments also increases in transceiver. Uplink of LTE advanced uses DFT-S OFDM using plural power amplifier. The effect of ICI increases in frequency domain of receiver due to phase noise and IQ imbalance. In this paper, we analyze influences of ICI in frequency domain of receiver considering phase noise and IQ imbalance in multiband system. Also, we separate phase noise and IQ imbalance effect from channel response in frequency domain of uplink system. And we propose a method to estimate the channel exactly and to compensate IQ imbalance and phase noise. Simulation result shows that the proposed method achieves the 2 dB performance gain of BER=$10^{-4}$.

• Applied Biological Chemistry
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• v.47 no.3
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• pp.300-306
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• 2004

Eight cation or anion-responsive polymer membranes were prepared by a casting procedure employing polyvinyl chloride, Bis (2-ethylhexyl)sebacate and each electroactive material in the ratio of 66 : 33 : 1. The resulting membranes were separately installed onto the sensitive area of the ionic electrodes to produce an 8-channel taste sensor array. The taste sensors of the array were connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a PC via an A/D converter. The taste evaluation system was applied to a discriminant analysis on six groups of marketed beverages like sikhye, sujunggwa, tangerine juice, ume juice, ionic drink and green tea. When the signal data from the sensor array were analyzed by principal component analysis after normalization, the 1st, 2nd and 3rd principal component explained most of the total data variance. The six groups of the analyzed beverages were discriminated well in the three dimensional principal component space. The half of the five groups of the analyzed beverages was also discriminated in the two dimensional principal component plane.