• 한국수소및신에너지학회논문집
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• 제32권5호
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• pp.410-416
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• 2021

The initial electrochemical performance of ceramic fuel cell with thin-film electrolyte was evaluated in terms of peak power density ratio, open circuit voltage ratio, and activation/ohmic resistance ratios at 500℃. Hydrogen and air were used as anode fuel and cathode fuel, respectively. The peak power density ratio reduced as ~17% for 40 minutes, which rapidly decreased in the early stage of the performance evaluation but gradually decreased. The open circuit voltage ratio decreased with respect time; however, its time behavior was remarkably different with the reduction behavior of the peak power density ratio. The activation resistance ratio increased as ~15% for 40 minutes, which was almost similar with the time behavior of the peak power density ratio.

• 한국수소및신에너지학회논문집
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• 제32권5호
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• pp.340-346
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• 2021

The initial electrochemical performance of ceramic fuel cell with thin-film electrolyte fabricated by plasma-enhanced atomic layer deposition method was evaluated in terms of peak power density ratio, open circuit voltage ratio, and activation/ohmic resistance ratios at 500℃. Hydrogen and air were used as anode fuel and cathode fuel, respectively. The peak power density ratio reduced as ~52% for 30 min, which continually decreased as time increased but degradation rate gradually decreased. The open circuit voltage ratio decreased with respect time; however, its behavior was evidently different from the reduction behavior of the peak power density. The activation resistance ratio increased as ~127% for 30 min, which was almost similar with the reduction behavior of the peak power density ratio.

• Design & Manufacturing
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• 제17권1호
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• pp.64-69
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• 2023

This paper explores the impact of gate shape changes on the size and density of foamed cells in microcellular foam injection molding. Five different gate shapes were examined while varying the amount of nitrogen gas(N2) injected for foaming. Analysis of the results showed that while average values did not change significantly, deviation values decreased by approximately 65% for cell size and 56% for density when 3.5wt% of nitrogen gas was injected in the film gate. Further analysis was conducted to verify this phenomenon, revealing that the contact area between the gate and product had the greatest impact. Our findings indicate that to ensure uniform generation of foamed cells in microcellular foaming product design, a gate with a wide contact area should be secured.

• 한국생물공학회:학술대회논문집
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• 한국생물공학회 2003년도 생물공학의 동향(XII)
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• pp.428-432
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• 2003

이 연구는 전기화학적 배양법과 호기성 조건을 유지함으로써 Thiobacillus ferrooxidans의 밀도가 높게 유지될 수 있다는 것을 보여준다. 최적 pH는 $2.0{\pm}0.05$로 결정하고 1vvm의 Air를 공급하였다 전류와 전압은 0.15A, 4V로 유지하였고 Pt 전극에서 85%의 효율로 $Fe^{3+}$ 를 $Fe^{2+}$로 환원시켰다. 이러한 조건에의 배양에서 초기 건조셀 밀도 0.0025 g-dry cell/L에서 8일 후에는 0.0576 g-dry cell/L에 이르렀다. 이는 같은 조건에서 고전적인 배양법에 의한 것보다 7배가 높은 값이다.

• Journal of Microbiology and Biotechnology
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• 제19권12호
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• pp.1603-1611
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• 2009

High-cell-density cultivation of yeast was investigated using the agricultural waste products corn steep liquor (CSL) and molasses. The Saccharomyces cerevisiae KV-25 cell mass was significantly dependent on the ratio between C and N sources. The concentrations of molasses and CSL in the culture medium were statistically optimized at 10.25% (v/v) and 16.87% (v/v), respectively, by response surface methodology (RSM). Batch culture in a 5-l stirred tank reactor using the optimized medium resulted in a cell mass production of 36.5 g/l. In the fed-batch culture, the feed phase was preceded by a batch phase using the optimized medium, and a very high dried-cell-mass yield of 187.63 g/l was successfully attained by feeding a mixture of 20% (v/v) molasses and 80% (v/v) CSL at a rate of 22 ml/h. In this system, the production of cell mass depended mainly on the agitation speed, the composition of the feed medium, and the glucose level in the medium, but only slightly on the aeration rate.

• 전력전자학회논문지
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• 제23권3호
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• pp.217-224
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• 2018

In this study, the optimal design methods of soft-switching cell for high-voltage DC-DC converter (HDC) of fuel cell electric vehicles (FCEVs) is proposed for high efficiency and high power density. The appropriate soft-switching cell for FCEVs is chosen by analyzing the losses of HDC which adopts soft-switching cell. The proposed optimal design methods for the soft-switching cell are divided into two purposes which are improvement of efficiency and power density. Two kinds of design methods enable to improve fuel efficiency and cost, respectively. The proposed design methods are validated with the experimental results based on the specification and hardware used in actual FCEVs.

• Journal of Electrical Engineering and Technology
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• 제11권4호
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• pp.939-942
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• 2016

One of the most important characteristic curves of a solar cell is its current density-voltage (J-V) curve under AM1.5G insolation. Solar cell can be considered as a semiconductor diode, so a diode equivalent model was used to estimate its parameters from the J-V curve by numerical simulation. Active layer plays an important role in operation of a solar cell. We investigated the effect thicknesses and defect densities (N_d) of the active layer on the J-V curve. When the active layer thickness was varied (for N_d = 8×10¹⁷ cm^-3) from 800 nm to 100 nm, the reverse saturation current density (J_o) changed from 3.56×10^-5 A/cm² to 9.62×10^-11 A/cm² and its ideality factor (n) changed from 5.28 to 2.02. For a reduced defect density (N_d = 4×10¹⁵ cm^-3), the n remained within 1.45≤n≤1.92 for the same thickness range. A small increase in shunt resistance and almost no change in series resistance were observed in these cells. The low reverse saturation current density (J_o = 9.62×10^-11 A/cm²) and diode ideality factor (n = 2.02 or 1.45) were observed for amorphous silicon based solar cell with 100 nm thick active layer.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 춘계학술대회 논문집
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• pp.13-16
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• 2008

Solid oxide fuel cell(SOFC) is an electrochemical energy conversion system with high efficiency and low-emission of pollution. In order to reduce the operating temperature of SOFC system under $800^{\circ}C$, the thickness reduction of YSZ electrolyte to be as thin as possible, e.g., less than 10 ${\mu}m$ are considered with the microstructure control and optimum design of unit cell. Methods for reducing the thickness of YSZ electrolyte have been investigated in coin cell. Moreover, a large unit cell($8cm{\times}8cm$) for SOFC was fabricated using an anode-supported electrolyte assembly with a thinner electrolyte layer, which was prepared by a tape casting method with a co-sintering technique. we studied the design factors such as active layer, electrolyte thickness, cathode composition, etc,. by the coin type of unit cell ahead of the fabrication process of a large unit cell and also reviewed about the evaluation technique of a large size unit cell such as interconnect design, sealing materials and current collector and so forth. Electrochemical evaluations of the unit cells, including measurements such as power density and impedance, were performed and analyzed. Maximum power density and polarization impedance of coin cell were 0.34W/$cm^2$ and $0.45{\Omega}cm^2$ at $800^{\circ}C$, respectively. However, Maxium power density of a large unit cell($5cm{\times}5cm$) decreased to 0.21W/$cm^2$ at $800^{\circ}C$ due to the increase of ohmic resistance. However, It was found that the potential value of a large unit cell loaded by 0.22A/$cm^2$ showed 0.76V at 100hrs without the degradation of unit cell.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.