• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.12
• /
• pp.2273-2277
• /
• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• 한국정보통신설비학회:학술대회논문집
• /
• 2009.08a
• /
• pp.364-366
• /
• 2009

광 바이오 센서 시스템에서 Trans-Impedance amplifier (TIA)는 광검출기로부터 입력단으로 들어오는 미세한 전기 신호를 원하는 신호레벨까지 증폭하는 역할을 한다. TIA는 광 바이오 센서 시스템의 감도 (sensitivity)를 결정하는 매우 중요한 회로로 저잡음, 저전력, 낮은 입력 임피던스 등의 특성이 요구되어진다. 본 논문에서는 광 바이오 센서 시스템에서 요구되어 지는 저전력, 저잡음 성능을 구현하기 위하여 regulated cascode (RGC) TIA를 설계하였다. 본 연구에서는 기존 common gate (CG) 기법의 TIA에서 전류원 역할을 하는 current source를 저항으로 대체하고, local feedback stage를 이용하는 RGC TIA를 저잡음, 저전력 특성 및 회로 면적 감소의 장점을 갖도록 설계하였다.

• Proceedings of the KIPE Conference
• /
• 2015.11a
• /
• pp.5-6
• /
• 2015

본 논문은 GaN (Gallium Nitride) HEMT (High Electron Mobility Transistor) 소자의 동작 특성과 Normally-off형 p-GaN 및 cascode-GaN 소자의 구현 방식에 따른 차이점을 분석한다. 두 소자의 차이점에 따른 동작 특성을 비교하고 게이트 구동 시 고려되어야 할 설계 요소를 분석한다.

• Proceedings of the KIEE Conference
• /
• 2000.07e
• /
• pp.149-151
• /
• 2000

본 논문에서는 완전균형 상보형 적분기에서 그 이득과 단위이득 주파수 특성을 향상시킬 수 있는 high-swing cascode 구조를 이용한 새로운 적분기를 설계하였다. 설계된 high-swing cascode 적분기는 $0.25{\mu}m$ n-well CMOS 공정 파라미터를 이용하여 HSPICE 시뮬레이션 하였으면, 그 결과 제안된 회로는 2V 공급전압에서 전력소모는 1.04mW이고 차단주파수는 100MHz를 갖으며 이득은 51dB로서 이 적분기를 이용한 능동필터 설계시 요구조건인 40dB 이상의 이득 값을 만족한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.5B
• /
• pp.639-644
• /
• 2001

본 논문에서는 저전압(2V) 동작이 가능하도록 high-swing cascode 방식을 이용한 능동소자를 제안하고, 이를 이용하여 400MHz의 차단주파수 특성을 나타내는 저역통과 능동필터를 설계하였다. 제안된 적분기는 이득특성에 영향을 주는 트랜스컨덕스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25$\mu\textrm{m}$ CMOS n-well 공정 파라미터를 이용한 Hspice 시뮬레이션 결과, 제안된 적분기는 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위이득주파수 특성을 나타내었다. 또한 이를 이용하여 설계된 저역통과 능동필터는 400MHz의 차단주파수 특성을 나타내고 368MHz에서 416MHz까지 튜닝이 가능하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.768-776
• /
• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• ETRI Journal
• /
• v.29 no.5
• /
• pp.670-672
• /
• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.5 s.96
• /
• pp.482-487
• /
• 2005

In this paper, we propose the control method of output impedance of each cascode unit cell of distributed amplifier by connecting varactors in the gate-terminal of common gate. Compared to common source unit cell, cascode unit cell has many advantages such as high gain and high output impedance as well as negative resistance loading. But if the transistor model which is used in design is inaccurate and process parameter is changed, oscillation sometimes can occur at band edge in which the gain start to drop. Therefore, we need control circuit which can prevent oscillation, although the circuit has already fabricated, and varactor connected to gate-terminal of common gate of cascode gain cell can play that part. Measured result of fabricated distributed amplifier shows the capability of contol of gain characteristic by adjusting of value of varactors, this can guarantee the stability of the circuit. The gain is $8.92\pm0.82dB$ over 49 GHz, the group delay is $\pm9.3 psec$ over 41 GHz. All transistor which has $0.15{\mu}m$ gate length is GaAs based p-HEMT, and distributed amplifier is put together with 4 stages.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.5
• /
• pp.197-203
• /
• 2003

In this paper, we have presented millimeter-wave high conversion gain quadruple subharmonic mixers adopting the cascode harmonic generator The subharmonic mixers were successfully integrated by using 0.1 ${\mu}{\textrm}{m}$ GaAs pseudomorphic HEMTs(PHEMTs) and coplanar waveguide(CPW) structures. Measured output of 1st, 2nd and 4th harmonics of the fabricated cascode 4th harmonic generator are -21.42 dBm, -32.65 dBm and -13.45 dBm, respectively, for an input power of 10 dBm at 14.5 GHz. We showed that the highest conversion gain of 3.4 dB has obtained thus far at a LO power of 13 dBm from the fabricated subharmonic mixers. The millimeter-wave subharmonic mixer also ensure a high degree of isolation showing -53.6 dB in the LO-to-IF and -46.2 dB in the LO-to-RF, respectively, at a frequency of 14.5 GHz. The high conversion gain achieved in this work is the first report among the millimeter-wave subharmonic mixers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.6
• /
• pp.435-443
• /
• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.