• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.987-990
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• 2003

This paper presents a cross-coupled RF VCO with high-Q MEMS-based spiral inductors. Since the use of high-Q inductors is critical to VCO design, MEMS-based spiral inductors with the Q-factor of nearly 22 are used for the RF VCO with an active cascode current source. The RF VCO circuits including spiral inductors have been designed and simulated in GaAs MMIC-MEMS process. The simulation results of the VCO circuits showed the phase noise of -180dBc/Hz at an offset frequency of 500KHz. The RF VCO circuit simulatinon used 2mA DC current and 3.3V supply.

• 전자공학회논문지D
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• 제35D권4호
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• pp.1-8
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• 1998

An MMIC single-balanced upconverting mixer for PCS application has been successfully developed using an MMIC process employed by 1 .mu. ion implanted GaAs MESFET and passive lumped elements consisting of spiral inductor, Si3N4 MIM capacitors and NiCr resistors. The configuration of the mixer presented in this paper is two balanced cascode FET mixers with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit including two active baluns intermodulation characteristic with two-tone excitation are also measured, showing -28.17 dBc at IF power of -30 dBm.

• 전자공학회논문지C
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• 제34C권10호
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• 전자공학회논문지C
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• 제34C권9호
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.754-759
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• 2016

A transformer feedback low-noise amplifier (LNA) is implemented in a standard $0.18{\mu}m$ CMOS process, which exploits drain-to-gate transformer feedback technique for wideband input matching and operates across entire 3~5 GHz ultra-wideband (UWB). The proposed LNA achieves power gain above 9.5 dB, input return loss less than 15.0 dB, and noise figure below 4.8 dB, while consuming 8.1 mW from a 1.8-V supply. To the authors' knowledge, drain-to-gate transformer feedback for wideband input matching cascode LNA is the first adopted technique for UWB application.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2001년도 종합학술발표회 논문집 Vol.11 No.1
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• pp.227-230
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• 2001

본 논문은 마이크로파 슈퍼헤테로다인 수신기에서 발생되는 이미지성분을 효과적으로 제거하기위한 Cascode형 FETs구조를 이용한 Ku-Band 이미지 제거용 자기발진믹서을 분석하였다. 자기발진믹서는 두개의 FET에 의해서 동작되며 상위 FET는 유전체공진기에 의해서 발진기로 동작하며, 아래쪽 FET는 믹서로 동작시켰다. 모의실험 결과 초기 게이트바이어스 전압은 $V_{ gsl}$=-0.4V와 $V_{g2}$=-0.4V와 $V_{g2}$V선정 하였으며, 10.75GHz의 발진기 출력은 2.249dBm, 위상잡음은 -137.9dBc/1000KHz, 이미지 제거특성은 약 -26dBc 값을 얻었다.얻었다.

• 한국전자파학회지:전자파기술
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• 제14권4호
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• pp.23-30
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• 2003

본 고에서는 마이크로파 대역에서 우수한 전력특성을 보이는 GaAs HBT를 이용한 광대역 고출력 전력증폭기 설계에 대하여 살펴본다. GaAs HBT의 전력 소자로서의 장점과 설계시 고려해야 할 단위 전력 소자의 설계, 열적 안정성 문제, 바이어스 회로설계, 그리고 광대역 설계 기법에 대하여 간단히 소개한다. 그리고, 본 연구에서 2~6 GHz 광대역 고출력 전력증폭기를 캐스코드(cascode) HBT를 이용하여 설계하였다. 측정 결과, 2 W의 평균 출력 전력, 10 dB의 이득, 24~43 %의 전력 부가 효율을 얻을 수 있었으며, 칩 크기는 $1.6{\times}2.4 mm^2$로서 매우 작았다. 이 결과를 기존에 개발된 GaAs HBT 광대역 고출력 전력증폭기와 비교 분석하였으며, 칩 면적당 대역폭과 출력 전력, 효율이 아주 우수함을 알 수 있다.