• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.231-233
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• 1991

This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• 전기의세계
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• v.11
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• pp.8-13
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• 1963

Solid state nuclear radiation detector에 사용되는 transistor에 의한 저잡음 charge sensitive preamplifier의 설계방식과 이에 대한 실측결과에 관하여 기술하였다. 먼저 transistor noise의 제원인을 분석하고 이 잡음들을 최소로 하기 위하여 이에 관련된 각 parameter에 대하여 이론 및 실험적으로 고찰하였다. 지금까지 알려진 진공관식 증폭기의 최소잡음은 등가전자수로 표시하면 약 250전자 정도이고 그 transistor증폭기에 있어서는 약 1,000전자 정도이었으나 본 설계방식에 의하여 제작된 transistor증폭기에서는 detector를 포함한 전 input capacitance가 약 100PF일때 약 400전자의 양호한 저잡음특성을 보이고 있으며 linearity 및 stability도 매우 좋은 결과를 보이고 있다. 여기에 사용된 cascode회로 자체는 이미 오래 전부터 알려져 있었지만 잡음을 최소로 하기 위한 설계방법은 지금껏 알려지지 않고 있으므로 본 논문에서는 전치증복기의 소요이득에서 잡음을 최소로 할 수 있는 설계방식을 확립하여 이 방식에 의한 실측결과는 종래의 transistor를 사용한 것보다 가장 좋았다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.559-560
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• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.521-522
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• 2008

This paper presents fully integrated low power consumption limiting amplifier. The proposed limiting amplifier is employed folded cascode structure with source degeneration output stage. This proposed structure demands few transconductance than conventional structure. It can be dramatically decrease current consumption. The total power consumption is only $96.5\;{\mu}W$ under a 1.8 V supply voltage in 9.5 dB limited gain condition. It was designed in using $0.18\;{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1046-1049
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• 2002

In this paper, a sub-harmonic dual-gate FET mixer for IMT-2000 base-station was designed by using single-gate FET cascode structure and driven by the second order harmonic component of LO signal. The dual-gate FET mixer has the characteristic of high conversion gain and good isolation between ports. Sub-harmonic mixing is frequently used to extend RF bandwidth for fixed LO frequency or to make LO frequency lower. Furthermore, the LO-to-RF isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer because the frequency separation between the RE and LO frequency is large. As RF power is -30dBm and LO power is 0dBm, the designed mixer shows the -47.17dBm LO-to-RF leakage power level, 10dB conversion gain, -0.5dBm OIP3, -10.5dBm IIP3 and -1dBm 1dB gain compression point.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.