• Title/Summary/Keyword: Capacitance coupling

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Analysis of Factors Impacting Atmospheric Pressure Plasma Polishing

  • Zhang, Ju-Fan;Wang, Bo;Dong, Shen
    • International Journal of Precision Engineering and Manufacturing
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    • v.9 no.2
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    • pp.39-43
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    • 2008
  • Atmospheric pressure plasma polishing (APPP) is a noncontact precision machining technology that uses low temperature plasma chemical reactions to perform atom-scale material removal. APPP is a complicated process, which is affected by many factors. Through a preliminary theoretical analysis and simulation, we confirmed that some of the key factors are the radio frequency (RF) power, the working distance, and the gas ratio. We studied the influence of the RF power and gas ratio on the removal rate using atomic emission spectroscopy, and determined the removal profiles in actual operation using a commercial form talysurf. The experimental results agreed closely with the theoretical simulations and confirmed the effect of the working distance. Finally, we determined the element compositions of the machined surfaces under different gas ratios using X-ray photoelectron spectroscopy to study the influence of the gas ratio in more detail. We achieved a surface roughness of Ra 0.6 nm on silicon wafers with a peak removal rate of approximately 32 $mm^{3}$/min.

Lumped Element MMIC Direction Coupler Based on Parallel Coupled-Line Theory (평행 결합선로 이론에 근거한 MMIC 집중 소자형 방향성 결합기)

  • Kang Myung-Soo;Park Jun-Seok;Lee Jae-Hak;Kim Hyeong-Seok
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.11
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    • pp.577-582
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    • 2004
  • In this paper, lumped equivalent circuits for a conventional parallel directional coupler are proposed. This equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of parallel-coupled line. By using the derived design formula, we have designed the 3dB and 4.7dB MMIC couplers at the center frequency of 3.4GHz and 5.6GHz respectively. Measurements for the designed MMIC directional couplers show at 4dB and 5.2dB-coupling value at the center frequency of 3.4GHz and 5.6GHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper

Analysis of Stepped Impedance Lowpass Filter with Coupled Open Stubs (개방스텁을 갖는 계단 임피던스 저역통과 필터의 해석)

  • 김성일;기철식;박익모;임한조
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.10
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    • pp.1078-1082
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    • 2002
  • In this paper, we have studied the dependence of insertion loss of a microstrip stepped impedance lowpass filter with coupled open stubs. Coupling mechanisms in the filter depend not only on the transmission line width of the filter but also the gap width of coupled open stubs and three attenuation poles are created with the proper conditions. Also edge capacitance between open stubs play an important role in having three attenuation Poles. We verify the results by obtaining [S] matrices.

Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature

  • Boubaker, Aimen;Sghaier, Nabil;Souifi, Abdelkader;Kalboussi, Adel
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.143-151
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    • 2010
  • In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

High Performance Circuit Design of a Capacitive Type Fingerprint Sensor Signal Processing (고성능 용량 형 지문센서 신호처리 회로 설계)

  • 정승민;이문기
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.109-114
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    • 2004
  • This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

A Study on the PCB Design of a CAT.5E Modular Jacks Employing Field Cancellation Techniques (PCB에서 필드 상쇄 기법을 적용한 Cat. 5E급 모듈라잭 설계에 관한 연구)

  • 류대우;이중근
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.1
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    • pp.136-142
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    • 2001
  • In this paper, a method of canceling and suppressing differential mode crosstalk noise signals caused by non-uniform coupling between two transmission lines in UTP (unshielded twisted pair) modular jacks is discussed. Differential mode crosstalk noise signals in balanced transmission lines with UTP modular jacks were suppressed, by applying field cancellation techniques to this modular jack. To verify an effectiveness of the field cancellation techniques, 8 pin modular jacks were made, and the NEXT (Near End Crosstalk) losses were measured to prove its applicability by the network analyzer(HP8720C) at 100 Mb/s.

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A Low-Loss On-Chip Transformer Using an Auxiliary Primary Part (APP) for CMOS Power Amplifier Applications

  • Im, Haemin;Park, Changkun
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.403-406
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    • 2019
  • We propose a low-loss on-chip transformer using an auxiliary primary part (APP) for an output matching network for fully integrated CMOS power amplifiers. The APP is designed using a fifth metal layer while the primary and secondary parts are designed using a sixth metal layer with a width smaller than that of the primary and secondary parts of the transformer to minimize the substrate loss and the parasitic capacitance between the primary and secondary parts. By adapting the APP in the on-chip transformer, we obtain an improved maximum available gain value without the need for any additional chip area. The feasibility of the proposed APP structure is successfully verified.

Numerical study of topological SQUIDs

  • Soohong, Choi;Yeongmin, Jang;Sara, Arif;Yong-Joo, Doh
    • Progress in Superconductivity and Cryogenics
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    • v.24 no.4
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    • pp.11-15
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    • 2022
  • We conducted numerical calculations to obtain the critical current as a function of the magnetic flux through the topologically trivial and non-trivial superconducting quantum interference devices (SQUIDs), with varying the capacitive and inductive couplings of Josephson junctions (JJs). Our calculation results indicate that a nontrivial SQUID is almost indistinguishable from trivial SQUID, considering the effective capacitance coupling. When the SQUID contains 2π- and 4π-periodic supercurrents, the periodicity of the current-flux relation can be distinguished from the purely trivial or nontrivial SQUID cases, and its difference is sensitive to the relative ratio between the topologically trivial and nontrivial supercurrents. We believe that our calculation results would provide a practical guide to quantitatively measure the portion of the topologically nontrivial supercurrents in experiments.

Low Voltage Swing BUS Driver and Interface Analysis for Low Power Consumption (전력소모 감소를 위한 저 전압 BUS 구동과 인터페이스 분석)

  • Lee Ho-Seok;Kim Lee-Sup
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.7
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    • pp.10-16
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    • 1999
  • This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

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A Study on the location of Compensation Capacitor and Capacitance in the Concrete Slab Track (콘크리트 슬래브궤도에서 보상 커패시터의 위치 및 전기용량에 대한 연구)

  • Kim, Min-Seok;Lee, Sang-Hyeok;Ko, Jun-Seog;Lee, Jong-Woo;Jo, Su-Ik;Yu, Jin-Young
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.879-891
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    • 2009
  • Impedance of rails is increased by the magnetic coupling between rails and reinforcing bars in the concrete slab track. Currently, the current of track circuit has been compensated by installing the compensation capacitors on track circuit because of increasing the impedance of rails. In case of a rapid transit railway, the compensation capacitors are installed every 20[m] to compensate the current of track circuit in the concrete slab track. Because the interval of one block for a rapid transit railway is as long as 1500[m], the compensation capacitors are installed about the number of 70$\sim$75 on track circuit. However, in case the compensation capacitors are broken over the number of three, it is a problem that the amplitude of current is under standard amplitude of current which is 0.8[A]. In this paper, it was suggested installing a compensation capacitor by using resonance phenomenon on the concrete slab track. We represent the electrical model of track circuit and the four terminal network, calculate the parameters demanded for the electrical model in the concrete slab track. Also, we computed the position and capacitance of the compensation capacitor about 2040[Hz], 2400[Hz], 2760[Hz], 3120[Hz] which currently is the track circuit frequency in the Gyeongbu rapid transit railway and demonstrated the validity of it, using the Matlab and PSpice program.

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