• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.6
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• pp.88-94
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• 2013

This paper proposes a capacitive touch switch using a switched-capacitor. The proposed method charges capacitance for measurement using the switched-capacitor until the voltage across the capacitance reaches a threshold voltage. As the proposed method uses the number of times being charged to measure the capacitance, the method has no relation with the operating frequency of the switched-capacitor. This paper also shows the quantization resolution of the proposed method is related to the capacitance in the switched-capacitor and the threshold voltage, i.e., the resolution is improved when the capacitance in the switched-capacitor is decreased and the threshold voltage is increased. Simulation result shows the method gives 31fF quantization resolution when the capacitance in the switched-capacitor is 50fF and threshold voltage is 80% of the supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.1-6
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• 2004

For MOSFET devices with nanometer range gate length, accurate extraction of effective gate length is highly important because transistor characteristics become very sensitive to effective channel length. In this paper, we propose a new approach to extract the effective channel length of nanometer range MOSFET by Capacitance Voltage(C-V) method. The effective channel length is extracted using gate to source/drain capacitance( $C_{gsd}$). It is shown that 1/$\beta$ method, Terada method and other C-V method are inadequate to extract the accurate effective channel length. Therefore, the proposed method is highly effective for extraction of effective channel length of 100nm CMOSFETs.s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.653-661
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• 2016

This paper proposes a capacitance estimation method of the dc-link capacitor for brushless DC motor (BLDCM) drive systems. In order to estimate the dc-link capacitance, the BLDCM is operated in quadrant-II or -IV among four-quadrant operation. Quadrant-II and -IV are called reverse braking and forward braking, respectively. During the braking operation of the BLDCM, the capacitor is charged by the phase current and then the voltage is increased during the braking operation time. The capacitor current and voltage can be obtained by using the phase current sensor of BLDCM and the dc-link voltage sensor. The capacitance and be easily obtained by the voltage equation of the capacitor. The proposed method guarantees the reliable and simple calculation of the dc-link capacitance without additional hardware system except several the sensors already installed for the motor control system. The effectiveness of the proposed method is verified through both the simulation and experimental results.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.1
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• pp.47-53
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• 2022

This paper proposes a method for selecting the capacitance of DC-link capacitors of inverters. In general, the DC-link capacitance of the inverter system must be considered for DC-link voltage, ripple current, switching frequency, ripple voltage, and pulse-width modulation techniques. Therefore, the appropriate capacitance can be determined by finding the rms and peak values of the ripple current of the capacitor. In this paper, the process of extracting the ripple current of DC-link capacitor is described in detail. In addition, the simple method for finding DC-link capacitor capacitance using the result value is presented through the simulations.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.679-682
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• 2003

Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.522-530
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• 2018

This study proposes the mitigation method of shaft voltage by varying the parasitic capacitance. First, the shaft voltage explained. Second, the parasitic capacitances causing shaft voltage are analyzed respect to geometry of motor and windings. Then, the equivalent circuit is established to obtain the shaft voltage and output torque characteristic and develope appropriate motor structure. Finally, simulation and experiment are conducted to verify that modified motor suppress the shaft voltage. This novel model does not require additional hardware.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.134-141
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• 2006

A potential transformer(PT) has ratio error and phase angle error. Precise measurement of the errors of PT can be achieved using high voltage capacitance bridge, high voltage capacitor and low voltage capacitor. The uncertainty for this method is evaluated and found to be $20{\times}10^{-6}$ in both ratio error and phase angle error. The values measured for PT using the method are well consistent with the those measured for same PT in NMIA(National Measurement Institute of Australia) within the corresponding uncertainty.

• Transactions on Electrical and Electronic Materials
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• v.14 no.4
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• pp.177-181
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• 2013

In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.