• Journal of the Ergonomics Society of Korea
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• v.36 no.2
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• pp.69-86
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• 2017

Objective: The present study is intended to develop an improved bus seat armrest design by evaluating various bus armrest designs from ergonomic aspects. Background: An ergonomic armrest design which considers the sitting postures and body shapes of passengers can improve the convenience and comfort of a bus seat. Method: Subjective satisfaction of each of five design dimensions (length, width, height from seatpan, shape, and angle) was evaluated for seven bus seat armrest designs in various sizes and shapes by 58 participants (28 males and 33 females) using a 7-point scale (1: very dissatisfied, 4: neutral, and 7: very satisfied). Improved bus seat armrest designs adjustable in length and rotatable to the left or right (sliding and rotating armrest, SRA) with a concave, flat, or convex shape of the upper part were developed by considering the preferred design features and the body size and shape in sitting posture and needs of passengers and then compared with a conventional armrest. Results: A bus seat armrest with a wide width (40~50mm), a long length (360mm), a lower height (213mm), and a curved shape was found significantly preferred in terms of comfort. The proposed armrest designs (SRA-convex, SRA-flat, and SRA-concave) improved satisfaction by 46~62% for length suitability, 184~216% for width suitability, 205~214% for angle suitability, 138~181% for contact area suitability, and 49~64% for height suitability, 138~174% for comfort, and 93~111% for overall satisfaction. Conclusion: The preferred design features and passengers' needs of bus seat armrest were identified and the SRA designs were recommended for better usability. Application: The ergonomic design process of bus seat armrest employed in the present study can be applied to designing armrests in various vehicles for better convenience and comfort.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.3
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• pp.169-174
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• 2011

This paper provides Bus Information System(BIS) implementation based on the Smart-phone APPs using GPS information. Nearly all of recent smart-phones are equipped with the GPS feature. Bus driver's smart-phone can send the position information using its GPS information periodically and on events. On receiving those information, servers can process those into the information that can be used by individual users and bus stop information panel. The proposed BIS based on smart-phone APPs is expected to be used publicly with the special process that enables the smart-phone APPs only in the specific bus.

• Journal of Power Electronics
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• v.12 no.4
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• pp.567-577
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• 2012

This paper introduces a new scheme to balance the DC bus voltages of a cascaded H-bridge converter which is used as a Distribution Static Synchronous Series Compensator (D-SSSC) in electrical distribution network. The aim of D-SSSC is to control the power flow between two feeders from different substations. As a result of different cell losses and capacitors tolerance the cells DC bus voltage can deviate from their reference values. In the proposed scheme, by individually modifying the reference PWM signal for each cell, an effective balancing procedure is derived. The new balancing procedure needs only the line current sign and is independent of the main control strategy, which controls the total DC bus voltages of cascaded H-bridge. The effect of modulation index variation on the capacitor voltage is analytically derived for the proposed strategy. The proposed method takes advantages of phase shift carrier based modulation and can be applied for a cascaded H-bridge with any number of cells. Also the system is immune to loss of one cell and the presented procedure can keep balancing between the remaining cells. Simulation studies and experimental results validate the effectiveness of the proposed method in the balancing of DC bus voltages.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.12
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• pp.675-682
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• 2000

When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

• International Journal of Highway Engineering
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• v.17 no.6
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• pp.33-36
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• 2015

PURPOSES : It is desirable for buses to be parallel to the face of the bus shelter at a bus stop. In this way, passengers can safely use the buses without moving into the vehicle area. The study was a review of the current bus bay geometric guidelines, to determine whether they lead buses to stop parallel to the face of the bus shelter by analyzing vehicle trajectory. METHODS : A commercial software program for vehicle trajectory analysis was used under our assumptions about bus dimensions and geometric values. The final position of the bus was analyzed for multiple trajectory simulations, reflecting various geometric alternatives. RESULTS : Within the scope of the study, we concluded that the current design guidelines need to be revised by the design values suggested by the study. CONCLUSIONS : The results of the study suggested alternative design values for bus bay geometry, based on the assumption that buses should be parallel to the face of the bus shelter in order to prevent passengers from moving into the vehicle area.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.5D
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• pp.587-595
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• 2008

Many studies on bus scheduling optimization have been done from the 1960s to recent years for establishing rational bus schedule plan that can improve convenience of bus passengers and minimize unnecessary runs. After 2000, as part of the Intelligent Transport Systems (ITS), the importance of the schedule management and providing schedule information through bus schedule optimization has become a big issue, and much research is being done to develop optimization models that will increase bus passenger convenience and, on the side of bus management, minimize unnecessary bus operation. The purpose of this study is to calculate the optimal bus frequency and create a timetable for each bus stop by applying DTR or DTRC model that use data for each bus stop and route segment. Model verification process was implemented using data collected from bus management system (BMS) and integrated transit-fare card system for bus route of Seoul's No. 472 line. In order to evaluate the reliability and uncertainty of optimal solution, sensitivity analysis was implemented for the various parameters and assumptions used in the bus scheduling model.

• Journal of IKEEE
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• v.24 no.2
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• pp.665-668
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• 2020

When a node in automotive CAN bus is hacked, such node should be blocked to prevent severe danger in the car. In order to do that, such node should be uniquely identified. However, there is no way to identify individual nodes in a CAN bus. In this paper, a physical layer security method is proposed where individual nodes are identified by assigning unique ID to the nodes during booting process. The proposed method was implemented in a CAN controller using Verilog HDL, and it is verified that the node ID auto-setting and internal attack defense are successfully performed.