• Journal of Korea Foundry Society
• /
• v.42 no.5
• /
• pp.314-322
• /
• 2022

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.174-177
• /
• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.117-123
• /
• 2008

In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.

• Journal of Korea Foundry Society
• /
• v.42 no.2
• /
• pp.136-144
• /
• 2022

• Journal of Digital Contents Society
• /
• v.9 no.3
• /
• pp.471-481
• /
• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.11
• /
• pp.109-118
• /
• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2014.04a
• /
• pp.18-19
• /
• 2014

멀티프로세서 시스템 온칩 (MPSoC) 플랫폼은 고성능 임베디드 시스템을 위한 핵심 구성요소이다. MPSoC 를 구성하는 각각의 처리요소 (processing element, PE)는 대응하는 태스크의 연산 특징에 맞춤으로 최적화되어 있어야 한다. 갈수록 증가하는 고성능의 요구에 따라 동종 MPSoC 는 각각의 태스크 연산 특징에 최적화된 다양한 PE 를 보유한 이기종 MPSoC 로 발전되어 왔다. 따라서 이기종 MPSoC 의 코어들은 응용에 특화된 맞춤형 명령어 세트로 설계된다. 하지만 이러한 이기종성은 다양한 태스크로 구성된 응용들을 어떻게 서로 다른 특성을 지닌 PE 들에 매핑해야 최적의 시스템을 구성할 지를 결정해야 하는 부담을 컴파일러와 같은 툴에 지우고 있다. 잘못된 매핑은 시스템 성능을 현저히 저하시킬 소지가 있다. 본 연구에서는 멀티미디어 응용 태스크의 연산 패턴을 분석하여 최적의 태스크 매핑을 결정하는 기법을 제안하고 있다.

• Journal of the Mineralogical Society of Korea
• /
• v.19 no.3 s.49
• /
• pp.163-169
• /
• 2006

Mineralogy and geochemistry of the sediment core from the seamount (2710 m below the sea level) just south of the Antarctic Polar Front were examined to draw paleoceanographic information in glacial-interglacial cycles. Smectite was most abundant clay mineral associated with illite and chlorite. Its content was slightly higher below 170 cm, suggesting a boundary between isotope stage 4 and 5. Si, Zr, Cs, Th, REE, $K_{2}O$, and $Al_{2}O_{3}$ show complete antithetical distribution with respect to $CaCO_{3}$ through the core. $SiO_{2}$ maxima and $CaCO_{3}$ minima at depths of 24, 136, and 176 cm are probably correlated with massive influx of ice-rafted debris during the advance of Antarctic ice shelves. Ni, Cu, and Ba show rather little correlation with $SiO_{2}$, suggesting their relation to biogenic debris, precipitation from seawater, or hydrothermal input. Particularly, Ba maxima tend to lag $10{\sim}20cm$ after $SiO_{2}$ maxima, probably due to rapid increase of productivity following deglaciation.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.237-243
• /
• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.74-79
• /
• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.