• Title/Summary/Keyword: CMOS transistor

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A Study on the Circuit Analysis of Composite BiCMOS Transistor and the Design Methodology of BiCMOS Differential Amplifier (복합 BiCMOS 트랜지스터의 회로 분석 및 그로 구성된 차동 증폭기의 설계기법에 관한 연구)

  • 송민규;김민규;박성진;김원찬
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.9
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    • pp.1359-1368
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    • 1989
  • In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

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3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse

  • Kim, Jin-Bong;Lee, Kwy-Ro
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.205-210
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    • 2003
  • A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

A High-Density 64k-Bit One-Time Programmable ROM Array with 3-Transistor Cell Standard CMOS Gate-Oxide Antifuse

  • Cha, Hyouk-Kyu;Kim, Jin-Bong;Lee, Kwy-Ro
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.106-109
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    • 2004
  • A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

Detection of Stuck-Open Faults in BiCMOS Circuits using Gate Level Transition Faults (게이트 레벨 천이고장을 이용한 BiCMOS 회로의 Stuck-Open 고장 검출)

  • 신재흥;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.198-208
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    • 1995
  • BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

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A Symbolic Layout Generator for CMOS Standard Cells Using Artificial Intelligence Approach (인공지능 기법을 이용한 CMOS 표준셀의 심볼릭 레이아웃 발생기)

  • 유종근;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.6
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    • pp.1080-1086
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    • 1987
  • SLAGEN, a system for symbolic cell layout based on artificial intelligence approach, takes as input a transistor connection description of CMOS standard cells and environment information, and outputs a symbolic layout description. SLAGEN performas transistor grouping by a heuristic search method, in order to minimize the number of separations, and then performs group reordering and transistor reordering with an eye toward minimizing routing. Next, SLAGEN creates a rough initial routing in order to guarantee functionality and correctness, and then improve the initial routing by a rule-based approach.

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Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS (다중 문턱전압 CMOS를 이용한 저 전력 캐리 예측 가산기 설계)

  • Kim, Dong-Hwi;Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.5
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    • pp.243-248
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    • 2008
  • This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

The CMOS RF model parameter for high frequency communication circuit design (고주파통신회로 설계를 위한 CMOS RF 모델 파라미터)

  • 여지환
    • Journal of Korea Society of Industrial Information Systems
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    • v.6 no.3
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    • pp.123-127
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    • 2001
  • The prediction method of the parameter C/sub gs/ of CMOS transistor is proposed by calculating the mobil charge in inversion layer of COMS transistor. This parameter C/sub gs/ decided on the cutoff frequency in MOS transistor in RF range and coupled input and output. This parameter C/sub gs/ in RF range is very important parameter in small signal circuit model. This proposed method is contributed to developing software of extracting parameter value in equivalent circuit model. The method provide the important information to construct a RF nonlinear model for multifinger gate MOSFET. This method will be very valuable to develop a large signal MOSFET model for nonlinear RF IC design.

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High-Speed BiCMOS Comparator

  • Jirawath, Parnklang;Wanchana, Thongtungsai
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.510-510
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    • 2000
  • This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

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The Delay time of CMOS inverter gate cell for design on digital system (디지털 시스템설계를 위한 CMOS 인버터게이트 셀의 지연시간)

  • 여지환
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 2002.06a
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    • pp.195-199
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    • 2002
  • This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

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On the detection of short faults in BiCMOS circuits using current path graph (전류 경로 그래프를 이용한 BiCMOS회로의 단락고장 검출)

  • 신재흥;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.2
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    • pp.184-195
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    • 1996
  • Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

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