• ETRI Journal
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• v.28 no.2
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• pp.175-181
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• 2006

A new CMOS voltage-controlled fully-differential transconductor is presented. The basic structure of the proposed transconductor is based on a four-MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ${\pm}\;1\;V$ at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully-differential Gm-C low-pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using $0.35\;{\mu}m$ technology are also given.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1871-1874
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• 2002

This paper describes a realization of a linearized transconductor using a CMOS complementary pair. The proposed transconductor is driven by a grounded signal source. How to cancel the offset current is described, Moreover , how to control the transconductance is described . It is shown that power consumption of the proposed transconductor without the control circuit is about half as low as that of the conventional Wang’s OTA through computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.4
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• pp.20-30
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• 2001

A novel 200 MHz CMOS transconductor using translinear cells is proposed. The proposed transconductor consists of voltage followers and current followers based on translinear cells and a resistor. For wide applications, a single-input single-output, a single-Input differential-output, and a fully-differential transconductor are systematically designed, respectively. The theory of operation is described and computer simulation results are used to verify theoretical predictions. The results show that the fully-differential transconductor has a linear input voltage range of ${\pm}2.7$ V, a 3 dB frequency of 200 MHz, and a temperature coefficient of less than 41 $ppm/^{\circ}C$ at supply voltages of ${\pm}3$ V. In order to certify the applicability of the fully-differential transconductor, A ladder-type 3th-order cllitic low pass filter is also designed based on the inductance simulation method. The filter has a ripple bandwidth of 22 MHz, a pass-band ripple of 0.36 dB, and a cutoff frequency of 26 MHz.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.348-351
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• 2001

In this paper, the Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback(CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using TSMC $0.35{\mu}m$ CMOS n-well parameters. The simulation results show 138kHz cutoff frequency and 11.05mW power dissipation with a 3.3V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.57-62
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• 1998

In this paper, tunable transconductor shows good linearity over a wide input voltage range are proposed. The proposed transconductor employ operating in the nonsaturation(ie., linear) region to improve circuit simplicity and tunability and 6.8V$\_$p-p/ wide input range. Also the circuit employ source-coupled differential pair to provide true differential input and can achieve both positive and negative transconductance values. The proposed circuits are implemented using a 1.2 $\mu\textrm{m}$ single poly double metal n-well CMOS technology. The THD characteristic of proposed circuit is less than 1% for a differential input voltage of up to 6V$\^$p-p/ when supply bias condition is V$\_$DD/=-V$\_$ss/=5V, I$\_$B/=20, 40${\mu}$A, and frequency of input signal is 1KHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.65-73
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• 2002

Two CMOS composite transistors with an improved operating region by reducing the threshold voltage are proposed in this paper. And also, as an application of the proposed composite transistors, the transconductor is designed. The proposed composite transistor I and II employ a P-type folded composite transistor and a composite diode in order to decrease the threshold voltage, respectively. The limitation of the operating region of these transistors by current source is described. All circuits are simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1526-1531
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• 2009

This paper describes the design of a 5th order Elliptic CMOS Gm-C low-voltage filter for the RFID reader IC. The designed filter is composed of CMOS differential transconductors by parallel gain circuits to improve the gain of the conventional self-biased differential amplifier. The filter is designed to operate in low-voltage 1.8V to meet the specification of the RFID reader filter. The results of HSPICE simulation using 1.8V-0.18${\mu}m$CMOS processing parameter showed that the designed 5th order Elliptic low-pass filter satisfied the cutoff frequency of 1.35MHz given by the design specification.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.424-427
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• 2007

A fully differential transconductor using the series composite transistor is proposed. Simulation results show that THD is less than 1.2% for the differential input signal of up to $1.5V_{p-p}$ when the input signal frequency is 10MHz. i he proposed transconductor is used to design a third-order elliptic Gm-C lowpass filter with 138kHz cutoff frequency for ADSL Tx filter. The design procedure is based on signal flow graph(SFG) of a doubly-terminated LC ladder filter by means of fully differential transconductors and capacitors. The filter is fabricated and measured with a $0.35{\mu}m$ CMOS process.

• ETRI Journal
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• v.31 no.5
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• pp.576-584
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• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.244-247
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• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.