Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of A CMOS Composite Transconductor for Low-voltage Low-power

저전압 저전력 CMOS복합 트랜스컨덕터 설계

  • 이근호 (전주대학교 정보기술컴퓨터공학부)
  • Published : 2002.10.01
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Abstract

Two CMOS composite transistors with an improved operating region by reducing the threshold voltage are proposed in this paper. And also, as an application of the proposed composite transistors, the transconductor is designed. The proposed composite transistor I and II employ a P-type folded composite transistor and a composite diode in order to decrease the threshold voltage, respectively. The limitation of the operating region of these transistors by current source is described. All circuits are simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well process.

두 가지 방식을 이용하여 넓은 동작 영역을 갖는 복합 트랜지스터를 제안하고, 이를 이용하여 새로운 트랜스컨덕터를 설계하였다. 저전압 저전력 특성을 위해 첫 번째 제안한 복합 트랜지스터 I은 P형 폴디드(P-type folded) 복합 트랜지스터를 이용하였으며, 복합 트랜지스터Ⅱ는 복합 다이오드 방식을 이용하여 문턱전압을 감소하였다. 이와 더불어 제안된 트랜지스터가 전류원에 의해 동작 영역이 제한되는 원인을 고찰하였으며, 응용 회로로 설계된 트랜스컨덕터의 특성을 해석하였다. 설계된 회로는 0.2㎛ CMOS n-well 공정 파라미터를 이용하여 HSPICE 시뮬레이션 하였다.

Keywords

References

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